TLK2501

1.5 TO 2.5 GBPS TRANSCEIVER

SLLS427D − AUGUST 2000 − REVISED JULY 2003

15

POST OFFICE BOX 655303

reference clock (GTX_CLK) timing requirements over recommended operating conditions (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Frequency

Minimum data rate

Typ −0.01%

75

Typ+0.01%

MHz

Frequency

Maximum data rate

Typ −0.01%

125

Typ+0.01%

MHz

Frequency tolerance

− 100

ppm

Duty cycle

40%

50%

60%

%

Jitter

Peak-to-peak

40

ps

TTL input electrical characteristics over recommended operating conditions (unless otherwise

noted), TTL signals: TXDO−TXD15, GTX_CLK, LOOPEN, LCKREFN, PRBSEN

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

VIH

High-level input voltage

See Figure 10

1.7

3.6

V

VIL

Low-level input voltage

See Figure 10

0.80

V

IIH

Input high current

VDD = MAX, VIN = 2 V

40

µA

IIL

Input low current

VDD = MAX, VIN = 0.4 V

−40

µA

CI

Input capacitance

0.8 V to 2 V

4

pF

tr

Rise time, GTX_CLK, TX_EN, TX_ER, TXD

0.8 V to 2 V, C = 5 pF,

See Figure 10

1

ns

tf

Fall time, GTX_CLK, TX_EN, TX_ER, TXD

2 V to 0.8 V, C = 5 pF,

See Figure 10

1

ns

tsu

TXD, TX_EN, TX_ER setup to

↑ GTX_CLK

See Figure 10

1.5

ns

th

TXD, TX_EN, TX_ER hold to

↑ GTX_CLK

See Figure 10

0.4

ns

TXD(0−15)

2.0 V

0.8 V

2.0 V

0.8 V

GTX_CLK

TX_ER, TX_EN,

tsu

th

tf

tr

0 V

3.6 V

0 V

3.6 V

tr

tf

Figure 10. TTL Data Input Valid Levels for AC Measurements