LM49321, LM49321RLEVAL

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SNAS457C – SEPTEMBER 2008 – REVISED MAY 2013

PLL N DIVIDER CONFIGURATION REGISTER

This register is used to control PLL N divider.

Bits

Register

Description

7:0

PLL_N

Programs the PLL feedback divider:

PLL_N

Divide Ratio

00000000

Divider Off

00000001

→00001010

10

00001011

11

00001100

12

...

...

11111000

248

11111001

249

(1)

The N divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The N

divider should never be set so that (Fin/M) * N > 55MHz (or 80MHz if FAST_VCO is set in the PLL_N_MOD register).

The non-sigma-delta division of the N divider is derived from the PLL_N as such:

N = PLL_N

PLL P DIVIDER CONFIGURATION REGISTER

This register is used to control the PLL's P divider.

Bits

Register

Description

3:0

PLL_P

Programs the PLL input divider to select:

0000

Divider Off

0001

1

0010

1.5

0011

2

...

–> 2.5

1101

7

1110

7.5

1111

8

(1)

The output of this divider should be either 12 or 24MHz in USB mode or 11.2896MHz, 12.288MHz or 24.576MHz in non-USB modes.

The division of the P divider is derived from PLL_P as such:

P = (PLL_P+1) / 2

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