STV7697B datasheet(8/18 Pages) STMICROELECTRONICS

8 / 18 page

Circuit Description

STV7697B

8/18

All the data are kept memorized in the latch stage when the strobe input (STB) is pulled high.

The Blanking input (BLK) forces the power outputs to high level when pulled high with polarity input

(POL) at high level and forced to low level with POL at low level. The level of the power output is

inverted when the polarity command (POL) is pulled high.

Driver outputs can be simultaneously polarized at high or low level depending on the biasing of the

POL input signal (Table 6).

Sustain current must not be sunk in the power output to VPP when the power supply is applied.

VSSLOG and VSSSUB must be connected as close as possible to the logical reference ground of the

application.

*Pn is the parallel output of the shift register (n = 1 to 64). Pn takes the value of serial input (SIN) after “n” shift

clock periods.

Table 6: Power Output Truth Table

CLR

STB

BLK

POL

Driver

Output

Comments

All H

Forced to High

All L

Forced to Low

Copy Data

Copy Inverted Data

Data Latched

Inverted Data Latched

All Low

All High

STV7697B Datasheet(PDF) 8 Page - STMicroelectronics