TUSB5052 datasheet(50/82 Pages) TI

50 / 82 page

7−2

7.1.3

LCR[2:1]: Line Control Registers (2 Registers)

These registers control the data communication format. The word length, number of stop bits, and parity type are

selected by writing the appropriate bits to the LCR.

FEN

BRK

FPTY

EPRTY

PRTY

STP

WL1

WL0

R/W

BIT

NAME

RESET

FUNCTION

1−0

WL[1:0]

Specifies the word length for transmit and receive.

00b = 5 bits

01b = 6 bits

10b = 7 bits

11b = 8 bits

STP

Specifies the number of stop bits for transmit and receive.

STP = 0 1 stop bit (word length = 5, 6, 7, 8)

STP = 1 1.5 stop bits (word length = 5)

STP = 1 2 stop bits (word length = 6, 7, 8)

PRTY

Specifies whether parity is used.

PRTY = 0 No parity

PRTY = 1 Parity is generated.

EPRTY

Specifies whether even or odd parity is generated.

EPRTY = 0 Odd parity is generated (if PRTY = 1).

EPRTY = 1 Even parity is generated (if PRTY = 1).

FPTY

Selects the forced parity bit

FPTY = 0 Parity is not forced.

FPTY = 1 Parity bit is forced. If EPRTY = 0, the parity bit is forced to 1.

BRK

This bit is the break-control bit.

BRK = 0 Normal operation

BRK = 1 Forces SOUT into break condition (logic 0)

FEN

FIFO enable. This bit is used to disable/enable the FIFO. To reset the FIFO, the MCU clears and then sets this bit.

FEN

FEN = 0

The FIFO is cleared and disabled. When disabled the selected receiver flow control is activated.

FEN = 1

The FIFO is enabled and it can receive data.

TUSB5052 Datasheet(PDF) 50 Page - Texas Instruments

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