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LMF100CIWM Datasheet(PDF) 8 Page - Texas Instruments |
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LMF100CIWM Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 42 page  Not Recommended for New Designs LMF100 SNOSBG9B – JULY 1999 – REVISED JUNE 2015 www.ti.com Electrical Characteristics for V + = +2.5 V and V− = −2.5 V (continued) The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100 k, R2 = 10 k), V + = +2.50 V and V− = −2.50 V unless otherwise specified. All limits are TA = TJ = 25°C unless otherwise specified. LMF100CCN LMF100CIWM PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX RL = 5 k 1.6 1.6 All Outputs −2.2 −2.2 ±1.5 Tested V Limit (1) RL = 5 k (All TMIN to TMAX ±1.4 VOUT Minimum output voltage swing Outputs) Design TMIN to TMAX ±1.4 Limit (2) 1.5 1.5 RL = 3.5 k V All Outputs −2.1 −2.1 GB Operational amplifier gain BW 5 5 MHz W product SR Operational amplifier slew rate 18 18 V/µs Source All Outputs 10 10 mA Maximum output, Isc Short circuit current (8) Sink All Outputs 20 20 mA (8) The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions. 6.7 Logic Input Characteristics All limits apply to TA = TJ = 25°C unless otherwise specified. LMF100CCN LMF100CIWM PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX 3 Tested Limit (1) MIN Logical “1” TMIN to TMAX 3 V V + = +5 V, V− = −5 V, Design Limit (2) TMIN to TMAX 3 −3 Tested Limit (1) MAX Logical “0” VLSh = 0 V TMIN to TMAX –3 V Design Limit (2) TMIN to TMAX −3 CMOS Clock Input Voltage 8 Tested Limit (1) MIN Logical “1” TMIN to TMAX 8 V V + = +10 V, V− = 0 V, Design Limit (2) TMIN to TMAX 8 2 Tested Limit (1) MAX Logical “0” VLSh = +5 V TMIN to TMAX 2 V Design Limit (2) TMIN to TMAX 2 2 Tested Limit (1) MIN Logical “1” TMIN to TMAX 2 V V + = +5 V, V− = −5 V, Design Limit (2) TMIN to TMAX 2 0.8 Tested Limit (1) MAX Logical “0” VLSh = 0 V TMIN to TMAX 0.8 V Design Limit (2) TMIN to TMAX 0.8 TTL Clock Input Voltage 2 Tested Limit (1) MIN Logical “1” TMIN to TMAX 2 V V + = +10 V, V− = 0 V, Design Limit (2) TMIN to TMAX 2 0.8 Tested Limit (1) MAX Logical “0” VLSh = 0 V TMIN to TMAX 0.8 V Design Limit (2) TMIN to TMAX 0.8 (1) Tested limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level). (2) Design limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level) but are not 100% tested. 8 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMF100 |
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