DDC_SDA

Start Condition (S)

Stop Condition (P)

DDC_SCL

DDC_SCL

1

2

3

4

5

6

7

8

9

DDC_SDA

1

2

3

4

5

6

7

8

9

2

3

4

5

6

7

1

Slave Address

MSB

Sub Address

Data

Stop

TFP501

SLDS127C

– JULY 2001 – REVISED JULY 2011

www.ti.com

The basic access cycle consists of the following:

•

A start condition

•

A slave address cycle

•

A subaddress cycle

•

Any number of data cycles

•

A stop condition

The start and stop conditions are shown in Figure 16. The high to low transition of DDC_SDA while DDC_SCL is

high defines the start condition. The low to high transition of DDC_SDA while DDC_SCL is high defines the stop

condition. Each cycle, (data or address) consists of 8 bits of serial data followed by one acknowledge bit

generated by the receiving device. Thus, each data/address cycle contains 9 bits as shown in Figure 17.

acknowledge by pulling the DDC_SDA line low during the ninth clock cycle if it decodes the address as its

address. During subsequent subaddress and data cycles the TFP501 responds with acknowledge as shown in

Figure 18. The subaddress is autoincremented after each data cycle.

The transmitting device must not drive the DDC_SDA signal during the acknowledge cycle so that the receiving

device may drive the DDC_SDA signal low. The not acknowledge, A, condition is indicated by the master by

keeping the DDC_SDA signal high just before it asserts the stop, P, condition. This sequence terminates a read

cycle as shown in Figure 19.

The slave address consists of 7 bits of address along with 1 bit of read/write information as shown below in

Figure 18, Figure 19, and Figure 20. For the TFP501, the possible slave addresses (including the r/w bit) are

0x74, 0x76 for write cycles and 0x75 and 0x77 for read cycles. Refer to the register description section for

additional base address information.

In order to minimize the number of bits that must be transferred for the link integrity check, a second read format

is supported. This format, shown in Figure 20, has an implicit subaddress equal to 0x08, the starting location of

18

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© 2001–2011, Texas Instruments Incorporated