CHIPSET

MEMORY

-

+

SD

GND

50k

50k

+

-

LP2996A

SNOSCY7 – JUNE 2014

www.ti.com

7 Detailed Description

7.1 Overview

The LP2996A linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-

device contains a high-speed operational amplifier to provide excellent response to load transients. The output

stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the

application as required for DDR-SDRAM termination.

7.2 Functional Block Diagram

7.3 Feature Description

The LP2996A is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2. The

output stage has been designed to maintain excellent load regulation while preventing shoot through. The

LP2996A also incorporates two distinct power rails that separates the analog circuitry from the power output

stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the

LP2996A to provide a termination solution for DDR2-SDRAM, DDR3-SDRAM and DDR3L-SDRAM memory. For

wide temperature designs, the LP2998/8Q is recommended for all DDR applications.

7.4 Device Functional Modes

The LP2996A can also be used to provide a termination voltage for other logic schemes such as SSTL-3 or

HSTL. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission

across the memory bus. This termination scheme is essential to prevent data error from signal reflections while

transmitting at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class

requirements from the LP2996A. This implementation can be seen below in Figure 16.

Figure 16. SSTL-Termination Scheme

10

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