LP2996

GND

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SD

LP2996

GND

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LP2996

GND

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SD

SD

LP2996-N

SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013

www.ti.com

Figure 24. Recommended SSTL-2 Implementation

If power dissipation or efficiency is a major concern then the LP2996-N has the ability to operate on split power

rails. The output stage (PVIN) can be operated on a lower rail such as 1.8V and the analog circuitry (AVIN) can

be connected to a higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered

reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications.

Increasing the output capacitance can also help if periods of large load transients will be encountered.

Figure 25. Lower Power Dissipation SSTL-2 Implementation

The third option for SSTL-2 applications in the situation that a 1.8V rail is not available and it is not desirable to

use 2.5V, is to connect the LP2996-N power rail to 3.3V. In this situation AVIN will be limited to operation on the

3.3V or 5V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum

continuous output current at the downside of higher thermal dissipation. Care should be taken to prevent the

LP2996-N from experiencing large current levels which cause the junction temperature to exceed the maximum.

Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3V

rail.

Figure 26. SSTL-2 Implementation with higher voltage rails

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