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LP2996M/NOPB Datasheet(PDF) 14 Page - Texas Instruments |
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LP2996M/NOPB Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 28 page  VTT LP2996 PVIN VDDQ VREF AVIN VREF = 0.75V VSENSE GND + + + VDDQ = 1.5V VDD = 2.5V VTT = 0.75V SD SD CIN COUT CREF R1 LP2996 + + VDDQ VDD VTT VTT PVIN VDDQ GND AVIN VSENSE COUT CIN R2 R1 LP2996 + + VDDQ VDD VTT VTT PVIN VDDQ GND AVIN VSENSE COUT CIN R2 LP2996-N SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com Figure 29. Increasing VTT by Level Shifting Conversely, the R2 resistor can be placed between VSENSE and VDDQ to shift the VTT output lower than the internal reference voltage of VDDQ/2. The equations relating VTT and the resistors can be seen below: VTT = VDDQ/2 (1 - R1/R2) (12) Figure 30. Decreasing VTT by Level Shifting HSTL APPLICATIONS The LP2996-N can be easily adapted for HSTL applications by connecting VDDQ to the 1.5V rail. This will produce a VTT and VREF voltage of approximately 0.75V for the termination resistors. AVIN and PVIN should be connected to a 2.5V rail for optimal performance. Figure 31. HSTL Application QDR APPLICATIONS Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this increase in bus lines has the effect of increasing the current levels required for termination. The recommended approach in terminating multiple channels is to use a dedicated LP2996-N for each channel. This simplifies layout and reduces the internal power dissipation for each regulator. Separate VREF signals can be used for each DIMM bank from the corresponding regulator with the chipset reference provided by a local resistor divider or one of the LP2996-N signals. Because VREF and VTT are expected to track and the part to part variations are minor, there should be little difference between the reference signals of each LP2996-N. 14 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP2996-N |
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