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LP3954TL/NOPB Datasheet(PDF) 43 Page - Texas Instruments |
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LP3954TL/NOPB Datasheet(HTML) 43 Page - Texas Instruments |
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43 / 60 page ![]() LP3954 www.ti.com SNVS340D – JUNE 2005 – REVISED MARCH 2013 LP3954 Control Registers Table 3. LP3954 Control Register Names and Default Values ADDR REGISTER D7 D6 D5 D4 D3 D2 D1 D0 (HEX) 00 RGB Ctrl cc_rgb1 cc_rgb2 r1sw g1sw b1sw r2sw g2sw b2sw 1 1 0 0 0 0 0 0 07 Ext. PWM control wled1_4 wled5_6 r1_pwm g1_pwm b1_pwm r2_pwm g2_pwm b2_pwm _pwm _pwm 0 0 0 0 0 0 0 0 08 WLED control slope fade_sel en_fade displ en_w1_4 en_w5_6 0 0 0 0 0 0 09 WLED1-4 wled1_4[7:0] 0 0 0 0 0 0 0 0 0A WLED5-6 wled5_6[7:0] 0 0 0 0 0 0 0 0 0B Enables pwm_ nstby en_ en_ rgb_sel[1:0] sync boost autoload 0 0 0 1 0 0 0C ADC output data[7:0] 0 0 0 0 0 0 0 0 0D Boost output boost[7:0] 0 0 1 1 1 1 1 1 0E Boost_frq freq_sel[2:0] 1 1 1 10 HC_Flash hc_pwm fl_t[1:0] hc[1:0] en_ hcflash 0 0 0 0 0 0 11 Pattern gen ctrl rgb_start loop log 0 0 0 12 RGB1 max current ir1[1:0] ig1[1:0] ib1[1:0] 0 0 0 0 0 0 13 RGB2 max current ir2[1:0] ig2[1:0] ib2[1:0] 0 0 0 0 0 0 2A audio sync CTRL1 gain_sel[2:0] sync_mode en_agc en_sync input_sel[1:0] 0 0 0 0 0 0 1 1 2B audio sync CTRL2 en_avg mode_ctrl[1:0] speed_ctrl[1:0] 0 0 0 0 0 50 Command 1A r[2:0] g[2:0] cet[3:2] 0 0 0 0 0 0 0 0 51 Command 1B cet[1:0] b[2:0] tt[2:0] 0 0 0 0 0 0 0 0 52 Command 2A r[2:0] g[2:0] cet[3:2] 0 0 0 0 0 0 0 0 53 Command 2B cet[1:0] b[2:0] tt[2:0] 0 0 0 0 0 0 0 0 54 Command 3A r[2:0] g[2:0] cet[3:2] 0 0 0 0 0 0 0 0 55 Command 3B cet[1:0] b[2:0] tt[2:0] 0 0 0 0 0 0 0 0 56 Command 4A r[2:0] g[2:0] cet[3:2] 0 0 0 0 0 0 0 0 57 Command 4B cet[1:0] b[2:0] tt[2:0] 0 0 0 0 0 0 0 0 Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 43 Product Folder Links: LP3954 |
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