TM8LR64JFN 8 388 608 BY 64BIT

TM16LR64JFN 16 777 216 BY 64BIT

SYNCHRONOUS DYNAMIC RAM MODULES

SMMS710 − MAY 1998

4

POST OFFICE BOX 1443

dual-in-line memory module and components

The dual-in-line memory module and components include:

functional block diagram for the TM8LR64JFN

8

DQ[0:7]

8

CS

U0

CS

U4

R

R

S0

DQMB0

DQ[0:7]

DQMB4

DQ[32:39]

DQM

DQ[0:7]

DQM

RAS

RAS: SDRAM U[0:7]

CK0†

CK: U1, U5

CK1

C

SPD EEPROM

SA0

SA1

SA2

A0

A1

A2

SDA

8

DQ[0:7]

8

CS

U1

CS

U5

R

R

DQMB1

DQ[8:15]

DQMB5

DQ[40:47]

DQM

DQ[0:7]

DQM

R = 10

Ω

RC = 10 Ω

C = 10 pF

8

DQ[0:7]

8

CS

U2

CS

U6

R

R

S2

DQMB2

DQ[16:23]

DQMB6

DQ[48:55]

DQM

DQ[0:7]

DQM

8

DQ[0:7]

8

CS

U3

CS

U7

R

R

DQMB3

DQ[24:31]

DQMB7

DQ[56:63]

DQM

DQ[0:7]

DQM

CAS

CAS: SDRAM U[0:7]

WE

WE: SDRAM U[0:7]

CKE0

CKE: SDRAM U[0:7]

A[0:13]

A[0:13]: SDRAM U[0:7]

RC

RC

RC

VDD

VSS

One 0.1

µF and

One 0.01

µF

U[0:7]

U[0:7]

CK2†

CK: U2, U6

CK: U3, U7

CK3

C

RC

RC

RC

CK: U0, U4

SCL

WP

47 k

Ω

LEGEND:

CS

= Chip select

SPD

= Serial Presence Detect

† Additional 3.3 pF capacity is used to balance loads among clocks.