TM8LR64JFN 8 388 608 BY 64BIT

TM16LR64JFN 16 777 216 BY 64BIT

SYNCHRONOUS DYNAMIC RAM MODULES

SMMS710 − MAY 1998

9

POST OFFICE BOX 1443

’xLR64JFN-8

’xLR64JFN-8A

UNIT

MIN

MAX

MIN

MAX

UNIT

nHZP3

Delay time, DEAC or DCAB command to DQ in high-impedance

state

CAS latency = 3

3

3

cycles

nWCD Delay time, WRT command to first data in

0

0

0

0

cycles

nWR

Delay time, final data in of WRT operation to DEAC or DCAB command

1

1

cycles

† All references are made to the rising transition of CK unless otherwise noted.

‡ Specifications in this table represent a single SDRAM device.