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TMS320VC5503 Datasheet(PDF) 33 Page - Texas Instruments |
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TMS320VC5503 Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 126 page  Functional Overview 33 April 2004 − Revised January 2008 SPRS245J 3.3.1 DMA Channel Control Register (DMA_CCR) The channel control register (DMA_CCR) bit layouts are shown in Figure 3−4. 15 14 13 12 11 10 9 8 DST AMODE SRC AMODE END PROG Reserved REPEAT AUTO INIT R/W, 00 R/W, 00 R/W, 0 R, 0 R/W, 0 R/W, 0 76 54 0 EN PRIO FS SYNC R/W, 0 R/W, 0 R/W, 0 R/W, 00000 LEGEND: R = Read, W = Write, n = value after reset Figure 3−4. DMA_CCR Bit Locations The SYNC[4:0] bits specify the event that can initiate the DMA transfer for the corresponding DMA channel. The five bits allow several configurations as listed in Table 3−3. The bits are set to zero upon reset. For those synchronization modes with more than one peripheral listed, the Serial Port Mode bit field of the External Bus Selection Register dictates which peripheral event is actually connected to the DMA input. Table 3−3. Synchronization Control Function SYNC FIELD IN DMA_CCR SYNCHRONIZATION MODE 00000b No event synchronized 00001b McBSP 0 Receive Event (REVT0) 00010b McBSP 0 Transmit Event (XEVT0) 00011b Reserved. These bits should always be written with 0. 00100b Reserved. These bits should always be written with 0. 00101b McBSP1 Receive Event (REVT1) 00110b McBSP1 Transmit Event (XEVT1) 00111b Reserved. These bits should always be written with 0. 01000b Reserved. These bits should always be written with 0. 01001b McBSP2 Receive Event (REVT2) 01010b McBSP2 Transmit Event (XEVT2) 01011b Reserved. These bits should always be written with 0. 01100b Reserved. These bits should always be written with 0. 01101b Timer 0 Interrupt Event 01110b Timer 1 Interrupt Event 01111b External Interrupt 0 10000b External Interrupt 1 10001b External Interrupt 2 10010b External Interrupt 3 10011b External Interrupt 4 / I2C Receive Event (REVTI2C)† 10100b I2C Transmit Event (XEVTI2C) Other values Reserved (Do not use these values) † The I2C receive event (REVTI2C) and external interrupt 4 (INT4) share a synchronization input to the DMA. When the SYNC field of the DMA_CCR is set to 10011b, the logical OR of these two sources is used for DMA synchronization. |
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