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HV2802 Datasheet(PDF) 14 Page - Microchip Technology |
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HV2802 Datasheet(HTML) 14 Page - Microchip Technology |
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14 / 26 page ![]() HV2802/HV2902 DS20005449A-page 14 2015 Microchip Technology Inc. 4.0 DETAILED DESCRIPTION AND APPLICATION INFORMATION The high-voltage analog switches are used for multiplexing a piezoelectric transducer array in a probe to multiple channel transmitters (Tx) arrays in a medical ultrasound system. Figure 4-1 shows a typical medical ultrasound image system comprising 64-channels of transmit pulsers, 64-channels of receivers (LNA and ADC) and 64-channels of T/R switches connecting to 192 elements of an ultrasound transducer probe via a high-voltage analog switch array. FIGURE 4-1: Typical Medical Ultrasound Imaging System. The HV2802/HV2902 devices are comprised of two main circuitries: • A low-power CMOS digital serial interface powered by VDD to control the high-voltage analog switches • High-voltage bilateral analog switch. High-voltage supplies VPP and VNN are needed by the high-voltage level translation circuitry to control the states of the output high-voltage analog switches. In addition, each high-voltage analog switch can be independently controlled because each switch is controlled via a corresponding latch. A 32-bit shift register and 32 latches allow the user to serially load data into the registers, and after completion, to load the data onto the latches that control the states of the high-voltage analog switches. The HV2802/HV2902 have a digital serial interface consisting of logic signals, Data In (DIN), Clock (CLK), Data Out (DOUT), Latch Enable (LE) and Clear (CLR). The digital circuits are supplied by VDD and either a 3.3V or a 5V logic can be used. With a VDD = 5V supply, the serial clock frequency can operate up to 20 MHz. The data is shifted into the shift registers on the rising edge (low-to-high transition) of the clock. The switch configuration bit of SW31 is shifted in first and the switch configuration bit of SW0 is shifted in last. To avoid clock feedthrough, the latch enable input (LE) should remain high while the 32-bit data-in signal is shifted into the 32-bit register. After the valid 32-bit data complete shifting into the shift registers, the high-to-low transition of the LE signal transfers the contents of the shift register into the latches. Finally, setting the LE high again allows all the latches to keep the current state, while new data can now be shifted into the shift registers without upsetting the latches. It is recommended to change all the latch states at the same time through this method to avoid possible clock feedthrough noise. See Figure 4-2 for details. ADC ADC ADC FPGA Ctrl Logic VIDEO CPU MEMORY Tx Rx T/R Switch T/R Switch Rx Tx Tx Rx T/R Switch CH64 CH2 CH1 PZT Array HV 2XXX SW Array Tx / Rx Array E1 E65 E192 E128 E129 E2 E66 E130 E64 |
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