MCP2050 datasheet(12/40 Pages) MICROCHIP

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MCP2050

DS20002299C-page 12

 2012-2014 Microchip Technology Inc.

1.5

Internal Voltage Regulator

The MCP2050 has a positive regulator capable of

supplying +5.0V or +3.3V at up to 70 mA of load current

with tolerances of ±3% over the entire operating

temperature range of -40°C to +125°C. The regulator

uses an LDO design, is short-circuit-protected and will

turn the regulator output off if its output falls below the

Shutdown Voltage Threshold VSD.

With a load current of 70 mA, the minimum input-to-

output voltage differential required for the output to

remain in regulation is typically +0.5V (+1V maximum

over the full operating temperature range). Quiescent

current is less than 100 µA with a full 70 mA load

current when the input-to-output voltage differential is

greater than +3.00V.

Regarding the correlation between VBB, VREG and IDD,

refer to Figure 1-9 and Figure 1-10. When the input

voltage (VBB) drops below the differential needed to

provide stable regulation, the voltage regulator output

VREG will track the input down to approximately VOFF.

The regulator will turn off the output at this point. This

will allow PIC® microcontrollers, with internal POR

circuits, to generate a clean arming of the Power-on

Reset trip point. The MCP2050 will then monitor VBB

and turn on the regulator when VBB is above the

threshold of regulator turn-on voltage VON.

Under specific ambient temperature and battery

voltage range, the voltage regulator can output as high

as 150 mA current.

For current load capability of the voltage regulator, refer

to Figure 1-9 and Figure 1-10.

In Power-Down mode, the VBB monitor is turned off.

The regulator requires an external output bypass

capacitor for stability. See Figure 2-1 for correct

capacity and ESR for stable operation.

FIGURE 1-8:

VOLTAGE REGULATOR BLOCK DIAGRAM

Note:

The regulator overload current limit is

approximately 250 mA. The regulator

output voltage VREG is monitored. If

output voltage VREG is lower than VSD, the

voltage regulator will turn off. After a

recovery time of about 3 ms, the VREG will

be checked again. If there is no short

circuit, (VREG > VSD) then the voltage

regulator remains on.

Note:

A ceramic capacitor of at least 10 µF, or a

tantalum capacitor of at least 2.2 µF is

recommended for stability.

Warning:

In worst-case scenarios, the ceramic

capacitor may derate by 50%, based on

tolerance,

voltage

and

temperature.

Therefore, in order to ensure stability,

ceramic capacitors smaller than 10 µF may

require a small series resistance to meet the

ESR requirements, as shown in Table 1-4.

TABLE 1-4:

RECOMMENDED SERIES

RESISTANCE FOR CERAMIC

CAPACITORS

Resistance

Capacitor



1µF

0.47



2.2 µF

0.22



4.7 µF

0.1



6.8 µF

Pass

Element

Sampling

Network

Buffer

VREG

VBB

VSS

Fast

Transient

Loop

VREF

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