SENSE_OUT

VCC

SENSE

GND

ENABLE

3.3 V

LDO

TPS3895A

OUT

Microprocessor

I/O

CT

IN

SENSE_OUT

VCC

SENSE

GND

ENABLE

3.0 V

LDO

1.8 V

LDO

TPS3895A

OUT

OUT

CT

IN

IN

5 V

5 V

EN

3.3 V

EN

3.0 V

EN

1.8 V

TPS389

www.ti.com

SBVS172B – JULY 2011 – REVISED APRIL 2015

Typical Applications (continued)

Figure 29. Voltage Sequencing (5 V

→ 3.3 V → 3 V → 1.8 V)

9.2.4.1 Design Requirements

Three rails must be sequenced to ensure proper start-up sequencing. The TPS3895As must drive the ENABLE

pins of each LDO, and use a logic-high signal to signify that the supply preceding it is above the desired

operating voltage for that rail. The ENABLE pin of the TPS3895As must be controlled by a microprocessor to

allow it to be shut down even when the rails are above the threshold.

9.2.4.2 Detailed Design Procedure

proper operation of the DSP, CPU, FPGA, and so on). Also, ensure that the currents that flow from the monitored

If an output delay time is required for any of the TPS3895As, connect a capacitor from the CT pin of that

TPS3895A to GND; see the Output Delay Time Pin (CT) section for more information. If no CT caps are

connected, the delay time is 40 µs for each TPS3895A in the chain. Because each of the ENABLE pins is tied to

the TPS3895A that precedes it (other than the first device in the chain), at a minimum the total delay time is the

sum of all the delay times set by the CT pins.

Copyright © 2011–2015, Texas Instruments Incorporated

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