TPS3897PDRYT datasheet(7/31 Pages) TI1

7 / 31 page

IT+

hys

IT+

pd(r)

VCC

SENSE

ENABLE

d(A)

(POR)

pd(f)

d(OFF)

UVLO

SENSE_OUT

IT+

TPS389

www.ti.com

SBVS172B – JULY 2011 – REVISED APRIL 2015

7.6 Timing Requirements

MIN

TYP

MAX

UNIT

V(SENSE) rising, C(CT) =

µs

open

tpd(r)

SENSE (rising) to SENSE_OUT propagation delay

V(SENSE) rising, C(CT) =

190

0.047 µF

tpd(f)

SENSE (falling) to SENSE_OUT propagation delay

V(SENSE) falling

µs

Start-up delay(1)

µs

ENABLE pin minimum pulse duration

µs

ENABLE pin glitch rejection

100

ENABLE to SENSE_OUT delay time (output

ENABLE deasserted to

td(OFF)

200

disabled)

output deasserted

ENABLE asserted to output

td(P)

ENABLE to SENSE_OUT delay time (P version)

asserted delay

200

(P version)

ENABLE asserted to output

asserted delay

µs

(A version), C(CT) = open

td(A)

ENABLE to SENSE_OUT delay time (A version)

ENABLE asserted to output

asserted delay

190

(A version), C(CT) = 0.047

µF

(1)

During power on, VCC must exceed 1.7 V for at least 50 µs (plus propagation delay time, tpd(r)) before output is in the correct state.

Figure 1. TPS3895A and TPS3897A Timing

Submit Documentation Feedback

Product Folder Links: TPS389

TPS3897PDRYT Datasheet(PDF) 7 Page - Texas Instruments

TPS3897PDRYT Datasheet(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL