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DS90C031TM Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # DS90C031TM
Description  LVDS Quad CMOS Differential Line Driver
PDF  14 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DS90C031TM Datasheet(HTML) 4 Page - National Semiconductor (TI)

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Switching Characteristics (Continued)
V
CC = +5.0V, TA = +25˚C DS90C031T. (Notes 3, 4, 6, 9)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
TLH
Rise Time
0.35
1.5
ns
t
THL
Fall Time
0.35
1.5
ns
t
PHZ
Disable Time High to Z
R
L = 100Ω,
C
L =5pF
(
Figure 4 and Figure 5)
2.5
10
ns
t
PLZ
Disable Time Low to Z
2.5
10
ns
t
PZH
Enable Time Z to High
2.5
10
ns
t
PZL
Enable Time Z to Low
2.5
10
ns
Switching Characteristics
V
CC = +5.0V ± 10%,TA = −40˚C to +85˚C DS90C031T. (Notes 3, 4, 5, 6, 9)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHLD
Differential Propagation Delay High to Low
R
L = 100Ω,CL =5pF
(
Figure 2 and Figure 3)
0.5
2.0
3.5
ns
t
PLHD
Differential Propagation Delay Low to High
0.5
2.1
3.5
ns
t
SKD
Differential Skew |t
PHLD –tPLHD|
0
80
900
ps
t
SK1
Channel-to-Channel Skew (Note 4)
0
0.3
1.0
ns
t
SK2
Chip to Chip Skew (Note 5)
3.0
ns
t
TLH
Rise Time
0.35
2.0
ns
t
THL
Fall Time
0.35
2.0
ns
t
PHZ
Disable Time High to Z
R
L = 100Ω,
C
L =5pF
(
Figure 4 and Figure 5)
2.5
15
ns
t
PLZ
Disable Time Low to Z
2.5
15
ns
t
PZH
Enable Time Z to High
2.5
15
ns
t
PZL
Enable Time Z to Low
2.5
15
ns
Switching Characteristics
V
CC = +5.0V ± 10%,TA = −55˚C to +125˚C DS90C031E. (Notes 3, 4, 5, 6, 9, 10)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHLD
Differential Propagation Delay High to Low
R
L = 100Ω,CL =20pF
(
Figure 3)
C
L Connected between
each Output and GND
0.5
2.0
5.0
ns
t
PLHD
Differential Propagation Delay Low to High
0.5
2.1
5.0
ns
t
SKD
Differential Skew |t
PHLD –tPLHD|
0
0.08
3.0
ns
t
SK1
Channel-to-Channel Skew (Note 4)
0
0.3
3.0
ns
t
SK2
Chip to Chip Skew (Note 5)
4.5
ns
t
PHZ
Disable Time High to Z
R
L = 100Ω,
C
L =5pF
(
Figure 4 and Figure 5)
2.5
20
ns
t
PLZ
Disable Time Low to Z
2.5
20
ns
t
PZH
Enable Time Z to High
2.5
20
ns
t
PZL
Enable Time Z to Low
2.5
20
ns
Parameter Measurement Information
DS011946-3
FIGURE 1. Driver V
OD and VOS Test Circuit
www.national.com
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