DS90C031TM datasheet(6/14 Pages) NSC

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Parameter Measurement Information (Continued)

Typical Application

Applications Information

LVDS drivers and receivers are intended to be primarily used

in an uncomplicated point-to-point configuration as is shown

Figure 6. This configuration provides a clean signaling en-

vironment for the quick edge rates of the drivers. The re-

ceiver is connected to the driver through a balanced media

which may be a standard twisted pair cable, a parallel pair

cable, or simply PCB traces. Typically, the characteristic im-

pedance of the media is in the range of 100

Ω. A termination

resistor of 100

Ω should be selected to match the media, and

is located as close to the receiver input pins as possible. The

termination resistor converts the current sourced by the

driver into a voltage that is detected by the receiver. Other

configurations are possible such as a multi-receiver configu-

ration, but the effects of a mid-stream connector(s), cable

stub(s), and other impedance discontinuities as well as

ground shifting, noise margin limits, and total termination

loading must be taken into account.

The DS90C031 differential line driver is a balanced current

source design. A current mode driver, generally speaking

has a high output impedance and supplies a constant cur-

rent for a range of loads (a voltage mode driver on the other

hand supplies a constant voltage for a range of loads). Cur-

rent is switched through the load in one direction to produce

a logic state and in the other direction to produce the other

logic state. The typical output current is mere 3.4 mA, a mini-

mum of 2.5 mA, and a maximum of 4.5 mA. The current

mode requires (as discussed above) that a resistive termi-

nation be employed to terminate the signal and to complete

the loop as shown in

Figure 6. AC or unterminated configu-

rations are not allowed. The 3.4 mA loop current will develop

a differential voltage of 340 mV across the 100

Ω termination

resistor which the receiver detects with a 240 mV minimum

differential noise margin neglecting resistive line losses

(driven signal minus receiver threshold (340 mV – 100 mV =

240 mV)). The signal is centered around +1.2V (Driver Off-

set, V

OS) with respect to ground as shown inFigure 7. Note

that the steady-state voltage (V

SS) peak-to-peak swing is

twice the differential voltage (V

OD) and is typically 680 mV.

The current mode driver provides substantial benefits over

voltage mode drivers, such as an RS-422 driver. Its quies-

cent current remains relatively flat versus switching fre-

quency. Whereas the RS-422 voltage mode driver increases

exponentially in most case between 20 MHz–50 MHz. This

is due to the overlap current that flows between the rails of

the device when the internal gates switch. Whereas the cur-

rent mode driver switches a fixed current between its output

without any substantial overlap current. This is similar to

some ECL and PECL devices, but without the heavy static

CC requirements of the ECL/PECL designs. LVDS requires

80% less current than similar PECL devices. AC specifica-

tions for the driver are a tenfold improvement over other ex-

isting RS-422 drivers.

The TRI-STATE function allows the driver outputs to be dis-

abled, thus obtaining an even lower power state when the

transmission of data is not required.

DS011946-7

FIGURE 5. Driver TRI-STATE Delay Waveform

DS011946-8

FIGURE 6. Point-to-Point Application

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