LXT381II datasheet(18/36 Pages) INTEL

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LXT381 — Octal E1 Line Interface

Datasheet

3.0

JTAG Boundary Scan

3.1

Overview

The LXT381 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy

access to the interface pins for board testing purposes.

In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT381 also

includes analog test port capabilities. This feature provides access to the TIP and RING signals in

each channel (transmit and receive.) This way, the signal path integrity across the primary winding

of each coupling transformer can be tested.

3.2

Architecture

Figure 6 represents the LXT381 basic JTAG architecture.

The LXT381 JTAG architecture includes a TAP Test Access Port Controller, data registers and an

instruction register. The following paragraphs describe these blocks in detail.

Figure 6. LXT381 JTAG Architecture

MUX

TDO

TAP

Controller

TCK

TMS

TRST

TDI

Boundry Scan Data Register

BSR

Analog Port Scan Register

ASR

Device Identification Register

IDR

Bypass Register

BYR

Instruction Register

LXT381II Datasheet(PDF) 18 Page - Intel Corporation