LXT381II datasheet(24/36 Pages) INTEL

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LXT381 — Octal E1 Line Interface

Datasheet

3.3.2

Device Identification Register (IDR)

The IDR register provides access to the manufacturer number, part number and the LXT381

revision. The register is arranged per IEEE 1149.1 and is represented in Table 5. Data into the IDR

is shifted in LSB first

3.3.3

Bypass Register (BYR)

The Bypass Register is a 1 bit register that allows direct connection between the TDI input and the

TDO output.

3.3.4

Analog Port Scan Register (ASR)

The ASR is a 5 bit shift register used to control the analog test port at pins AT1, AT2. When the

INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects to

the ASR output. After 5 TCK rising edges, a 5 bit control code is loaded into the ASR. Data into

the ASR is shifted in LSB first.

Table 6 shows the 16 possible control codes and the corresponding operation on the analog port.

The Analog Test Port can be used to verify continuity across the coupling transformers primary

winding

RESERVED14

RESERVED15

RESERVED16

Table 4.

Boundary Scan Register (BSR) (Continued)

Bit #

Signal

I/O

Type

Bit

Symbol

Comments

Table 5.

Device Identification Register (IDR)

Bit #

Comments

31 - 28

Revision Number

27 - 12

Part Number

11 - 1

Manufacturer Number

0Set to ‘1’

Table 6.

Analog Port Scan Register (ASR)

ASR Control Code

AT1 Forces Voltage To:

AT2 Senses Voltage From:

11111

TTIP0

TRING0

11110

TTIP1

TRING1

11101

TTIP2

TRING2

11100

TTIP3

TRING3

11011

TTIP4

TRING4

11010

TTIP5

TRING5

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