MPC8272CVRB datasheet(54/56 Pages) MOTOROLA

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MPC8272 PowerQUICC II™ Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Document Revision History

0.1

9/2003

• Addition of the MPC8271 and the MPC8247 (these devices do not have a security engine)

• Table 5: Addition of note 2 to VIH

• Table 5: Changed IOL for 60x signals to 6.0 mA

• Modiﬁcation of note 1 for Table 15, Table 16, Table 17, and Table 18

• Table 19: Addition of ball AD9 to GND. In rev 0 of this document, AD8 was listed as assigned

to both CS5 and GND. AD8 is only assigned to CS5.

• Table 19: Addition of note 4 to Thermal0 (D19) and Thermal1(J3)

• Addition of ZQ package code to Figure 15

0.2

12/2003

• Table 1: New

• Table 2: New

• Table 4: Modiﬁcation of VDD and VCCSYN to 1.45–1.60 V

• Table 5: Addition of note 2 regarding TRST and PORESET (see VIH row of Table 5)

• Table 5 and Table 19: Addition of muxed signals

CPCI_HS_ES to PCI_REQ1 (AF14)

CPCI_HS_LED to PCI_GNT1 (AE13)

CPCI_HS_ENUM to PCI_GNT2 (AF21)

• Table 5 and Table 19: Modiﬁcation of PCI signal names for consistency with PCI signal names

on other PowerQUICC II devices:

PCI_CFG0 (PCI_HOST_EN) (AC21)

PCI_CFG1 (PCI_ARB_EN) (AE22)

PCI_CFG2 (DLL_ENABLE) (AE23)

PCI_PAR (AF12)

PCI_FRAME (AD15)

PCI_TRDY(AF16)

PCI_IRDY (AF15)

PCI_STOP (AE15)

DEVSEL (AE14)

PCI_IDSEL (AC17)

PCI_PERR (AD14)

PCI_SERR (AD13)

PCI_REQ0–2 (AAE20, AF14, AB14)

PCI_GNT0–2 (AD20, AE13, AF21)

PCI_RST (AF22)

PCI_INTA (AE21)

PCI_C0-3 (AE12, AF13, AC15, AE18)

PCI_AD0-31

• Table 5 and Table 19: Corrected assertion level (added “ “) PCI_HOST_EN (AC21) and

PCI_ARB_EN (AE22)

• Table 6: Addition of RθJT and note 4

• Sections 4.1–4.5 and 4.7 on thermal characteristics: New

• Section 7, “Clock Conﬁguration Modes”: Modiﬁcation to ﬁrst paragraph. Note that

PCI_MODCK is a bit in the Hard Reset Conﬁguration Word. It is not an input signal as it is in

the MPC8280 Family and MPC8260 Family.

• Addition of “Note: Temperature Reﬂow for the VR Package" on page 51

• Table 19: Addition of note 2 to TRST (E21) and PORESET (C24)

• Table 19: Removal of Thermal0 (D19) and Thermal1(J3). These pins are now “No connects.”

Note 4 unchanged.

• Table 19: Removal of Spare0 (AD24). This pin is now a “No connect.” Note 5 unchanged.

• Table 19: Addition of PCI_MODE (AD22). This pin was previously listed as “Ground.” Addition

of note 1.

Table 21. Document Revision History

Revision

Date

Substantive Changes

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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