NCP3235

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14

PROTECTION FEATURES

Hiccup Mode

The NCP3235 uses hiccup mode for over current

protection. Upon entering hiccup mode after a fault

detection, the NCP3235 turns off the high side and low side

FET’s and PG goes low. It waits for tHiccup ms before

reinitiating a soft−start. tHiccup is defined as four soft start

timeouts (tss). The equation for tss is shown in Equation 1.

OCP is the only active fault detection during the hiccup

mode soft start.

Over Voltage Protection (OVP)

When the voltage at the FB pin (VFB) is above the OVP

threshold for greater than 5

ms (typical), an OVP fault is set.

The high side FET (HSFET) will turn off and the low side

FET (LSFET) will turn on. The open−drain PG pull down

will turn on at that point as well, thus pulling PG low. Once

VFB has fallen below the Undervoltage Protection

Threshold (UVP), the device will enter hiccup/latch off

mode. If entering latch off mode after a fault detection, the

NCP3235 turns off the high side and turns on the low side

FET’s and PG goes low. The user has to toggle the input

power supply to restart the device.

Under Voltage Protection (UVP)

A UVP circuit monitors the VFB voltage to detect an

under voltage event. If the VFB voltage is below this

threshold for more than 20

ms, a UVP fault is set and the

device will enter hiccup mode.

Over Current Protection (OCP)

The NCP3235 over current protection scheme senses the

peak freewheeling current in the low−side FET (LSOCP)

after a blanking time of 150 ns as shown in Figure 29. The

low−side MOSFET drain to source voltage is compared

against the voltage of an internal temperature compensated

current source and a user−selected resistor RSET. The value

of RSET for a given OCP level is defined by the follow

equation:

RSET

+

i

LS

RDSON

4

i

SET

(eq. 2)

is an internal current source used to compensate the

temperature effects of on resistance of low−side MOSFET.

value. By doing this, OCP accuracy won’t be affected by the

variation of MOSFET RDSON. In case RSET is not

connected, the device switches the OCP threshold to a fixed

300 mV threshold.

After one OCP event is detected, the NCP3235 keeps the

high−side MOSFET off until the low−side MOSFET falls

below the trip point again and the high−side MOSFET turns

on in the next clock cycle. So the low−side over current

protection shows pulse skipping behavior. An internal OCP

counter will count up to 3 consecutive OCP events. After the

third consecutive count, the device enters hiccup/latch

mode. The scheme of LS OCP and hiccup mode protection

is described in Figure 29.

Thermal Shutdown (TSD)

The NCP3235 protects itself from overheating with an

internal thermal monitoring circuit. If the junction

temperature exceeds the thermal shutdown threshold both

the upper and lower MOSFETs will be shut OFF. Once the

temperature drops below the falling hysteresis threshold, the

voltage at the COMP pin will be pulled below the ramp

valley voltage and a soft−start will be initiated.

Power Good Monitor (PG)

NCP3235 monitors the output voltage and signal when the

output is out of regulation or during a non−regulated

pre−bias condition, or fault condition. When the output

voltage is within the OVP and UVP thresholds, the power

good pin is a high impedance output. If the NCP3235 detects

an OCP, OVP, UVP, TSD or is in soft start, it pulls PG pin

low. The PG pin is an open drain 5−mA pull down output.

Layout Guide

When laying out a power PCB for the NCP3235 there are

several key points.

General Layout Guide: these are the common techniques

for high frequency high power board layout design.

Base

component

placement:

High

current

path

components should be placed to keep the current path as

tight as possible. Placement of components on the bottom of

the board such as input or output decoupling can add loop

inductance.

Ground

Return

for

Power

and

Signals:

Solid,

uninterrupted ground planes must be present and adjacent to

the high current path.

Copper Shapes on Component Layers: Large copper

planes on one or multiple layers with adequate vias will

increase thermal transfer, reduce copper conduction losses,

and minimize loop inductance. Greater than 20 A designs

require 2~3 layer shapes or more, increasing the number of

layers will only improvement performance.

Via Placement for Power and Ground: Place enough vias

to adequately connect outer layers to inner layers for thermal

transfer and to minimize added inductance in layer

transition. Multiple vias should be placed near important

components like input and output ceramic capacitors.

Key Signal Routes: Do not route sensitive signals, such as

FB near or under noisy nets such as the switch node VSW

and BST node, to reduce noise coupling effects on the

sensitive lines.

To improve the Low−side OCP accuracy, users should use

single ground connection instead of separate analog ground

and power ground. Make sure that the inner layers (at least

2nd layer, 3rd layer and 4th layer) are dedicated for ground

plane. Do not use other copper planes to break or interrupt