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CY28343
Document #: 38-07369 Rev. *A
Page 7 of 10
Notes:
10. The tSKEW specification is only valid for equal loading of all outputs (30 pF lump-load). Measurement are acquired at 1.5V for 3.3V signals.
11. The test load is 30 pF lump-load.
12. TR/TF are measured at 0.4V to 2.4V.
Differential Parameter Measurement Information
Figure 1. Phase Error
Table 6. AC Parameters for SDRAM Outputs: VDD_3.3V = 2.5V ±5%, AVDD_3.3V = 3.3V ±5%, TA = 0°C to +70°C
Parameter
Description
Condition
Min
Typ
Max
Unit
fCLK
Operating Clock Frequency
VDD_3.3V = 3.3V ±5%
99
133
MHz
tDCI
Input Clock Duty Cycle
45
55
%
tLOCK[9]
Maximum PLL Lock Time
1.5
ms
tDCO
Output Clock Duty Cycle
100 MHz, 133 MHz
45
50
55
%
Tr/Tf[10, 11,
12]
Output Clocks Slew Rate
0.4
1.6
ps
tpZL, tpZH
Output Enable Time (all outputs)
3
5
ns
tpLZ, tpHZ
Output Disable Time (all outputs)
3
5
ns
tCCJ
Cycle-to-Cycle Jitter
@133 MHz
90
200
ps
tPHASE
Phase Error
@133 MHz
400
ps
tSKEW
Any Output to Any Output Skew[11]
200
ps
VOUT
Output Voltage Swing[11]
1.1
VDD – 0.4
V
Vx
Output Crossing Voltage[11]
(VDD/2) – 0.2
VDD/2
(VDD/2) + 0.2
V
t(∅)n+1
N
t()n =
n
=
N
t()n
( N is large num ber o f sam ples)
Σ
1
t(∅)n
CK_IN
FB IN
1.25V /1 .5 V
1.25V
1.2 5 V
∅
∅
1.25V /1 .5 V
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