CY28343 datasheet(1/10 Pages) CYPRESS

Part #	CY28343

Description	Zero Delay SDR/DDR Clock Buffer

PDF	10 Pages

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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Zero Delay SDR/DDR Clock Buffer

CY28343

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07369 Rev. *A

Revised December 26, 2002

Features

• Phase-lock loop clock distribution for DDR and SDR

SDRAM applications

• One-single-end clock input to 6 pairs DDR outputs or

13 SDR outputs.

• External feedback pins FBIN_SDR/FBOUT_SDR are

used to synchronize the outputs to the clock input for

SDR.

• External feedback pins FBIN_SDR/FBOUT_SDR are

used to synchronize the outputs to the clock input for

DDR.

• SMBus interface enables/disables outputs.

• Conforms to JEDEC SDR/DDR specifications

• Low jitter, low skew

• 48 pin SSOP package

Note:

1.

Pins marked with [*] have internal pull-down resistors. Pins marked with [**] have internal pull-up resistors.

Table 1. Function Table

SELDDR_SDR#

CLKIN

SDRAM(0:12)

DDRT/C(0:5)

FBIN_DDR

FBOUT_DDR

FBIN_SDR

FBOUT_SDR

1= DDR Mode

2.5V

Compatible

OFF

Active

2.5V

Compatible

2.5V

Compatible

Active

2.5V

Compatible

OFF

0 = SDRAM Mode

3.3V

Compatible

Active

3.3V

Compatible

OFF

Active

3.3V

Compatible

Active

3.3V

Compatible

Block Diagram

Pin Configuration[1]

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

VDD_3.3V

SDRAM0

SDRAM1

SDRAM2

SDRAM3

VSS

VDD_3.3V

SDRAM4

SDRAM5

CLKIN

SDRAM6

SDRAM7

VSS

VDD_3.3V

SDRAM8

SDRAM9

SDRAM10

SDRAM11

VSS

VDD_3.3V

SDRAM12

FBOUT_SDR

FBIN_SDR*

VSS

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

SELDDR_SDR#*

FBIN_DDR*

FBOUT_DDR

VDD_2.5V

DDRT5

DDRC5

DDRT4

DDRC4

VSS

VDD_2.5

DDRT3

DDRC3

DDRT2

DDRC2

VSS

VDD_2.5V

DDRT1

DDRC1

DDRT0

DDRC0

VSS

VDD_3.3V

SCLK**

SDATA**

FBOUT_DDR

DDRT(0:5)

DDRC(0:5)

Control

Logic

FBOUT_SDR

SDRAM(0:12)

SCLK

SDATA

PLL

*SELDDR_SDR

FBIN_DDR

CLKIN

FBIN_SDR

VDD_2.5V

VDD_3.3V

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