Data Sheet

10

Rev. 1.1, 2012-10-19

TLE8080EM

5V Supply, Reset and Supervision

Figure 4

Reset Timing Diagram

5.3

Watchdog Operation

The TLE8088EE integrates a watchdog function which monitors the correct SPI communication with the micro

controller. A watchdog disable pin ( WD_DIS ) with an internal pull down current source is implemented. With a

high level the watchdog function is disabled.

watchdog period is done with a low to high transition of the CSN pin of a valid transmission of a 16 bit message.

in Figure 5.

Status after watchdog overflow:

•

all outputs are switched off

•

SPI registers are not influenced

•

Watchdog Time Out bit in SPI status register is set

•

first answer to SPI communication is the content of the status register

Switching of Outputs and reset of Watchdog Time Out Bit after watchdog overflow:

•

Outputs 1 and 3 will be switched on with an positive edge at IN1 respectively IN3

•

Outputs 2, 4 and 5 will be switched on with a write command to CMD register

•

the watchdog time out bit will be reset with the rising edge of CSN of the first read command of the status

register

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