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TLE8080-2EM Datasheet(PDF) 25 Page - Infineon Technologies AG

Part # TLE8080-2EM
Description  Engine Management IC for Small Engines
PDF  39 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TLE8080-2EM Datasheet(HTML) 25 Page - Infineon Technologies AG

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TLE8080EM
Serial Peripheral Interface (SPI)
Data Sheet
25
Rev. 1.1, 2012-10-19
There are four ways of valid access:
•
Write access to the command register: the answer is 1 for the R/W bit, 00 for the address and the content of
the register
•
Read access to the command register: the answer is 0 for the R/W bit, 00 for the address and the content of
the register
•
Read access to the diagnosis register: the answer is 0 for the R/W bit, 01 for the address and the content of
the register
•
Read access to the status register: the answer is 0 for the R/W bit, 10 for the address and the content of the
register
Any other access is recognized as an invalid message.
Status Flag Indication: after the falling edge of CSN and before the first rising edge of SCLK, the level of the SO
indicates the status of the diagnosis register:
•
SO = “0”: no error condition detected; all diagnosis register bits are “0”
•
SO = “1”: one or more error conditions are detected; one or more diagnosis register bits are “1”
With this feature during every SPI communication a check of the diagnosis status can be done without additional
read access of the diagnosis register.
Figure 13
SPI Protocol
SPI Answers:
•
during power on reset: SPI commands are ignored, SO is always low
•
after power on reset: the content of the command register is transmitted with the next SPI transmission
•
during watchdog reset: SPI commands are ignored, SO has the value of the status flag
•
after watchdog overflow: the content of the status register is transmitted with the first SPI transmission after
the low to high transition of NRO
•
after a read or write command: the content of the selected register is transmitted with the next SPI transmission
•
after an invalid communication: the content of the diagnosis register is transmitted with the next SPI
transmission
Bit 15
MSB
Bit 0
LSB
don’t care
don’t care
clock
1
clock
2
clock
3
clock
15
clock
16
Bit 14
Bit 13
Bit 1
don’t care
Bit 0
LSB
Bit 15
MSB
Bit 14
tristate
tristate
time
time
time
time
don’t care
Bit 1
Bit 13
SCLK
SI
SO
CSN
Status
Flag
*)
*) active clock edge for reading data at SI



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