VPC3232D datasheet(54/78 Pages) MICRONAS

54 / 78 page

VPC 323xD, VPC 324xD

ADVANCE INFORMATION

Micronas

*) chroma selector must be set to 1 (CIN chroma select)

4.3. Pin Descriptions

(pin numbers for PQFP80 package)

Pins 1-3 – Analog Component Inputs RGB1/YCrCb1

(Fig. 4–11)

These are analog component inputs with fast blank

control. A RGB or YCrCb signal is converted using the

component AD converter. The input signals must be

AC-coupled.

Pins 4-6 – Analog Component Inputs RGB2/YCrCb2

(Fig. 4–11)

These are analog component inputs without fastblank

control. A RGB or YCrCb signal is converted using the

component AD converter. The input signals must be

AC-coupled.

Pin 7, 64 – Ground, Analog Shield Front-End GNDF

Pin 9 – Supply Voltage, Decoupling Circuitry VSUPCAP

This pin is connected with 220 nF/1.5 nF/390 pF to

GNDCAP.

Pin 10 – Supply Voltage, Digital Circuitry VSUPD

Pin 11 – Ground, Digital Circuitry GNDD

Pin 12 – Ground, Decoupling Circuitry GNDCAP

Pin 13– I2C Bus Clock SCL (Fig. 4–3)

This pin connects to the I2C bus clock line.

Pin 14– I2C Bus Data SDA (Fig. 4–12)

This pin connects to the I2C bus data line.

Pin 15 – Reset Input RESQ (Fig. 4–3)

A low level on this pin resets the VPC 32xx.

Pin 16 – Test Input TEST (Fig. 4–3)

This pin enables factory test modes. For normal opera-

tion, it must be connected to ground.

Pin 17 – VGAV-Input (Fig. 4–3)

This pin is connected to the vertical sync signal of a VGA

signal.

Pin 18 – YC Output Enable Input YCOEQ (Fig. 4–3)

A low level on this pin enables the luma and chroma

outputs.

Pin 19 – FIFO Input Enable FFIE (Fig. 4–4)

This pin is connected to the IE pin of the external field

memory.

Pin 20 – FIFO Write Enable FFWE (Fig. 4–4)

This pin is connected to the WE pin of the external field

memory.

Pin 21 – FIFO Reset Write/Read FFRSTW (Fig. 4–4)

This pin is connected to the RSTW pin of the external

field memory.

Pin 22 – FIFO Read Enable FFRE (Fig. 4–4)

This pin is connected to the RE pin of the external field

memory.

Pin 23 – FIFO Output Enable FFOE (Fig. 4–4)

This pin is connected to the OE pin of the external field

memory.

Pin 24 – Main Clock Output CLK20 (Fig. 4–4)

This is the 20.25 MHz main clock output.

Pin 25 – Ground, Analog Pad Circuitry GNDPA

Pin 26 – Supply Voltage, Analog Pad Circuitry VSUPPA

This pin is connected with 47 nF/1.5 nF to GNDPA

Pin 27 – Double Output Clock, LLC2 (Fig. 4–4)

Pin 28 – Output Clock, LLC1 (Fig. 4–4)

This is the clock reference for the luma, chroma, and

status outputs.

GNDAI

SUPPLYA

Ground, Analog Component Inputs Front-End

VREF

OUTPUT

Reference Voltage Top, Analog Component

Inputs Front-End

FB1IN

VREF

Fast Blank Input

AISGND

SUPPLYA

Signal Ground for Analog Component Inputs,

connect to GNDAI

8, 61

–

LV OR GNDD

Not connected

Pin No.

PQFP

80-pin

Pin Name

Type

Connection

(if not used

)

Short Description

VPC3232D Datasheet(PDF) 54 Page - Micronas

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