AD7873

Rev. D | Page 21 of 28

SERIAL INTERFACE

Figure 36 shows the typical operation of the serial interface of

the AD7873. The serial clock provides the conversion clock and

also controls the transfer of information to and from the

AD7873. One complete conversion can be achieved with 24

DCLK cycles.

The CS signal initiates the data transfer and conversion process.

The falling edge of CS takes the BUSY output and the serial bus

out of three-state. The first eight DCLK cycles are used to write

to the control register via the DIN pin. The control register is

updated in stages as each bit is clocked in. Once the converter

has enough information about the following conversion to set

the input multiplexer and switches appropriately, the converter

enters the acquisition mode and, if required, the internal switches

are turned on. During acquisition mode, the reference input

data is updated. After the three DCLK cycles of acquisition, the

control word is complete (the power management bits are now

updated) and the converter enters conversion mode. At this

point, track-and-hold goes into hold mode, the input signal is

sampled, and the BUSY output goes high (BUSY returns low on

the next falling edge of DCLK). The internal switches can also

turn off at this point if in single-ended mode, battery-monitor

mode, or temperature measurement mode.

The next 12 DCLK cycles are used to perform the conversion

and to clock out the conversion result. If the conversion is

ratiometric (SER/DFR low), the internal switches are on during

the conversion. A 13th DCLK cycle is needed to allow the

DSP/micro to clock in the LSB. Three more DCLK cycles clock

out the three trailing zeroes and complete the 24 DCLK transfer.

The 24 DCLK cycles can be provided from a DSP or via three

bursts of eight clock cycles from a microcontroller.

CS

DCLK

DIN

BUSY

DOUT

(SER/DFR HIGH)

(SER/DFR LOW)

THREE-STATE

(START)

IDLE

OFF

OFF

(MSB)

(LSB)

ON

ON

OFF

OFF

ACQUIRE

CONVERSION

IDLE

ZERO FILLED

THREE-STATE

THREE-STATE

THREE-STATE

1

888

11

10

9

8

7

6

5

4

3

2

1

0

1

1

S

A2

PD1 PD0

A1

DFR

NOTES

Figure 36. Conversion Timing, 24 DCLKS per Conversion Cycle, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.

CS

DCLK

DIN

BUSY

DOUT

DB11

PD0

DB10

Figure 37. Detail Timing Diagram