OMAP5912ZVLR datasheet(21/270 Pages) TI1

21 / 270 page

Features

December 2003 − Revised December 2005

SPRS231E

OMAP5912 Features

D Low-Power, High-Performance CMOS

Technology

− 0.13-

µm Technology

− 192-MHz Maximum Frequency

− 1.6

+ 5% V Core Voltage

D ARM926EJ-S (MPU) Core

− Support for 32-Bit and 16-Bit

(Thumb

 Mode) Instruction Sets

− 16K-Byte Instruction Cache

− 8K-Byte Data Cache

− Data and Program Memory Management

Unit (MMU)

− 17-Word Write Buffer

− Two 64-Entry Translation Look-Aside

Buffers (TLBs) for MMUs

D TMS320C55x (C55x) DSP Core

− One/Two Instructions Executed per Cycle

− Dual Multipliers

(Two Multiply-Accumulates per Cycle)

− Two Arithmetic/Logic Units

− Five Internal Data/Operand Buses

(3 Read Buses and 2 Write Buses)

− 32K x 16-Bit On-Chip Dual-Access RAM

(DARAM) (64K Bytes)

− 48K x 16-Bit On-Chip Single-Access RAM

(SARAM) (96K Bytes)

− Instruction Cache (24K Bytes)

− Video Hardware Accelerators for DCT,

iDCT, Pixel Interpolation, and Motion

Estimation for Video Compression

D 250K Bytes of Shared Internal SRAM

D Memory Traffic Controller (TC)

− 16-Bit EMIFS Supports up to 256M Bytes

of External Memory (i.e., Async.

ROM/RAM, NOR/NAND Flash, and Sync.

Burst Flash)

− 16-Bit EMIFF to Access up to 64M Bytes

of SDRAM, Mobile SDRAM, or

Mobile DDR

D DSP Memory Management Unit

D DSP Peripherals

− Three 32-Bit Timers and Watchdog Timer

− Six-Channel DMA Controller

− Two Multichannel Buffered Serial Ports

− Two Multichannel Serial Interfaces

D MPU Peripherals

− Three 32-Bit Timers and Watchdog Timer

− USB 1.1 Host and Client Controllers

− USB On-the-Go (OTG) Controller

− 3 USB Ports, One With an Integrated

Transceiver

− Camera Interface for Parallel CMOS

Sensors

− Real-Time Clock (RTC)

− Pulse-Width Tone (PWT) Interface

− Pulse-Width Light (PWL) Interface

− Keyboard Matrix Interface (6 x 5 or 8 x 8)

− HDQ/1-Wire

 Interface

− Multimedia Card (MMC) and Secure

Digital (SD) Interface

− Up to 16 MPU General-Purpose I/Os

− Two LED Pulse Generators (LPGs)

− ETM9

 Trace Module for ARM926EJ-S

Debug

− 16-/18-Bit LCD Controller With Dedicated

System DMA Channel

− 32-kHz Operating System (OS) Timer

D Shared Peripherals

− 8 General-Purpose Timers

− Serial Port Interface (SPI)

− Three Universal Asynchronous

Receiver/Transmitters (UARTs) (Two

Supporting SIR mode for IrDA)

− Inter-Integrated Circuit (I2C) Master and

Slave Interface

− Multimedia Card (MMC) and Secure

Digital (SD) Interface

− Multichannel Buffered Serial Port

− Up to 64 Shared General-Purpose I/Os

− 32-kHz Synchro Counter

D Endian Conversion Unit

D Hardware Accelerators for Cryptographic

Functions

− Random Number Generation

− DES and 3DES

− SHA-1 and MD5

D Individual Power-Saving Modes for

MPU/DSP/TC

D On-Chip Scan-Based Emulation Logic

D IEEE Std 1149.1† (JTAG) Boundary Scan

Logic

D Three 289-Ball BGA (Ball Grid Array)

Packages (ZDY and ZZG − Lead-Free;

GDY − With Lead)

All trademarks are the property of their respective owners.

† IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.

OMAP5912ZVLR Datasheet(PDF) 21 Page - Texas Instruments

OMAP5912ZVLR Datasheet(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL