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OMAP5912ZVLR Datasheet(PDF) 81 Page - Texas Instruments |
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OMAP5912ZVLR Datasheet(HTML) 81 Page - Texas Instruments |
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81 / 270 page  Introduction 81 December 2003 − Revised December 2005 SPRS231E 2.4 Signal Description Table 2−5 provides a description of the signals on OMAP5912. Many signals are available on multiple pins, depending upon the software configuration of the pin multiplexing options. Table 2−5. Signal Descriptions SIGNAL ZDY/ GDY BALL# ZZG BALL# DESCRIPTION TYPE† EXTERNAL MEMORY INTERFACE FAST (EMIFF) SDRAM INTERFACE SDRAM.CS E7 G8 SDRAM chip-select O SDRAM.DQSH A12 C14 DDR DQ strobe high I/O SDRAM.DQSL A2 D4 DDR DQ strobe low I/O SDRAM.CAS D5 B4 SDRAM column address strobe. SDRAM.CAS is active (low) during reads, writes, and the REFR and MRS commands to SDRAM memory. O SDRAM.DQML C7 C8 SDRAM lower data mask. Active-high data mask for the lower byte of the SDRAM data bus (SDRAM.D[7:0]). The data mask outputs allow for both 16-bit-wide and 8-bit-wide accesses to SDRAM memory. O SDRAM.DQMU A8 D10 SDRAM upper data mask. Active-high data mask for the upper byte of the SDRAM data bus (SDRAM.D[15:8]). The data mask outputs allow for both 16-bit-wide and 8-bit-wide accesses to SDRAM memory. O SDRAM.RAS D4 H7 SDRAM row address strobe. SDRAM.RAS is active (low) during ACTV, DCAB, REFR, and MRS commands to SDRAM memory. O SDRAM.WE E6 H8 SDRAM write enable. SDRAM.WE is active (low) during writes, DCAB, and MRS commands to SDRAM memory. O SDRAM.A[13:0] D10 E8 E9 F8 F9 C6 A10 E10 C8 D9 C3 F7 A1 B2 H11 H9 H10 B8 B12 G9 G11 G12 B9 G10 A1 B6 B2 A2 SDRAM address bus. Provides row and column address information to the SDRAM memory as well as MRS command data. SDRAM.A[10] also serves as a control signal to define specific commands to SDRAM memory. O SDRAM.BA[1:0] C4 C5 C3 B3 SDRAM bank address bus. Provides the bank address to SDRAM memories O SDRAM.D[15:0] B10 C10 B11 B9 A11 B8 B12 C9 B7 A3 B6 B3 A5 A4 B5 B4 C12 D12 D13 C11 C13 D11 D14 C10 D8 C4 C7 D5 D7 C5 C6 D6 SDRAM data bus. SDRAM.D[15:0] provides data exchange between the traffic controller and SDRAM memory. I/O SDRAM.CLK A7 C9 SDRAM clock. Clock for synchronization SDRAM memory commands/accesses. O SDRAM.CLKX A6 D9 DDR clock. Inverted clock for synchronization DDR memory commands/accesses O SDRAM.CKE B13 H12 SDRAM clock enable (active-high). Asserting this signal enables the SDRAM clock for normal operation; negating puts SDRAM memory into low-power mode. O † I = Input, O = Output, Z = High-Impedance ‡ GPIO13 is used to select between full and fast boot. Set GPIO13 high to boot from the USB peripheral. Set GPIO13 low to boot from external flash on CS3. |
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