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ML7041 Datasheet(PDF) 4 Page - LAPIS Semiconductor Co., Ltd. |
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ML7041 Datasheet(HTML) 4 Page - LAPIS Semiconductor Co., Ltd. |
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4 / 28 page  FEDL7041-05 ML7041 4/28 PIN DESCRIPTIONS Pin Symbol Type Description State in power-down mode 1 AG — Analog ground (0 V) — 2 EAR2O O Receive side voice amplifier output 2 High impedance 3 EAR1O O Receive side voice amplifier output 1 High impedance 4 VA1 — Analog power supply 1 (3.0 V) — 5 EXTO O Receive side voice amplifier output High impedance 6 EXTI I Receive side voice amplifier input — 7 VA2 — Analog power supply 2 (3.0 V) — 8 SPO– O Receive side voice amplifier output– High impedance 9 AG2 — Analog ground 2 (0 V) — 10 AG3 — Analog ground 3 (0 V) — 11 SPO+ O Receive side voice amplifier output+ High impedance 12 VA3 — Analog power supply 3 (3.0 V) — 13 AGGP1 — General purpose port ground 1 (0 V) — 14 GP1 O General purpose port 1 output (Open drain) High impedance 15 GP2 O General purpose port 2 output (Open drain) High impedance 16 GP3 O General purpose port 3 output (Open drain) High impedance 17 GP4 O General purpose port 4 output (Open drain) High impedance 18 AGGP2 — General purpose port ground 2 (0 V) — 19 VDD — Digital power supply (3.0 V) — 20 MCK I Master clock input (2.048 MHz) — 21 SDA I/O I 2C data input/output (Pull-up resister required) High impedance 22 SCL I I 2C shift clock input — 23 PCMIN I PCM receive signal input — 24 PCMOUT O PCM transmit signal output “H” 25 DG — Digital ground (0 V) — 26 BCLK I PCM data shift clock input — 27 SYNC I PCM data shift sync signal input — 28 PDN I Power down control input “L” 29 RG1PDN I Power down input for regulator 1 (3.0 V/0 V) “L” 30 RG2PDN I Power down input for regulator 2 (3.0 V/0 V) “L” 31 AGR1 — Ground for regulator 1 (0 V) — 32 RG1O O Regulator 1 output (3.0 V) “L” (RG1PDN = “L”) 33 RG1IN I Regulator 1 power input (3.6 V) — 34 AGR2 — Ground for regulator 2 (0 V) — 35 RG2O O Regulator 2 power output (3.0 V) “L” (RG2PDN = “L”) 36 RG2IN I Regulator 2 input (3.6 V) — 37 VA — Analog power supply (3.0 V) — 38 SWA I/O Analog switch A — 39 SWB I/O Analog switch B — 40 SWC I/O Analog switch C — 41 MIC1I I Transmit side amplifier 1 inverting input — 42 MIC1O O Transmit side amplifier 1 output High impedance 43 MIC2I I Transmit side amplifier 2 inverting input — 44 MIC2O O Transmit side amplifier 2 output High impedance 45 MIC3+ I Transmit side amplifier 3 non-inverting input — 46 MIC3– I Transmit side amplifier 3 inverting input — 47 MIC3O O Transmit side amplifier 3 output High impedance 48 SG O Analog signal ground (1.4 V) “L” |
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