ADPD103BCPZ datasheet(47/53 Pages) AD

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ADPD103

Data Sheet

Rev. B | Page 46 of 52

SYSTEM REGISTERS

Table 24. System Registers

Address

Data

Bit

Default Access Name

Description

0x00

[15:8]

0x00

R/W

FIFO_SAMPLES

FIFO status. Number of available bytes to be read from the FIFO. When

comparing this to the FIFO length threshold (Register 0x06, Bits[13:8]),

note that the FIFO status value is in bytes and the FIFO length threshold

is in words, where one word = two bytes.

With the FIFO_ACCESS_ENAbit set, write 1 to Bit 15 of FIFO_SAMPLES to

clear the contents of the FIFO.

0x0

R/W

Reserved

Write 0x1 to clear this bit to 0x0.

0x0

R/W

SLOTB_INT

Time Slot B interrupt. Describes the type of interrupt event. A 1 indicates

an interrupt of a particular event type has occurred. Write a 1 to clear the

corresponding interrupt. After clearing, the register goes to 0. Writing a 0

to this register has no effect.

0x0

R/W

SLOTA_INT

Time SlotAinterrupt. Describes the type of interrupt event.A1 indicates an

interrupt of a particular event type has occurred. Write a 1 to clear the

corresponding interrupt. After clearing, the register goes to 0. Writing a 0

to this register has no effect

[4:0]

0x00

R/W

Reserved

Write 0x1F to clear these bits to 0x00.

0x01

[15:9]

0x00

R/W

Reserved

Write 0x00.

0x0

R/W

FIFO_INT_MASK

Sends an interrupt when the FIFO data length has exceeded the FIFO

length threshold in Register 0x06, Bits[13:8]. A 0 enables the interrupt.

0x1

R/W

Reserved

Write 0x1.

0x1

R/W

SLOTB_INT_MASK

Sends an interrupt on the Time Slot B sample. Write a 1 to disable the

interrupt. Write a 0 to enable the interrupt.

0x1

R/W

SLOTA_INT_MASK

Sends an interrupt on the Time Slot A sample. Write a 1 to disable the

interrupt. Write a 0 to enable the interrupt.

[4:0]

0x1F

R/W

Reserved

Write 0x1F.

0x02

[15:3]

0x0000

R/W

Reserved

Write 0x0000.

0x0

R/W

INT_ENA

INT pin enable.

0: disable the INT pin. The INT pin floats regardless of interrupt status.

The status register (Address 0x00) remains active.

1: enable the INT pin.

0x0

R/W

INT_DRV

INT drive.

0: the INT pin is always driven.

1: the INT pin is driven when the interrupt is asserted; otherwise, it is left

floating and requires a pull-up or pull-down resistor, depending on

polarity (operates as open drain). Use this setting if multiple devices

need to share the INT pin.

0x0

R/W

INT_POL

INT polarity.

0: the INT pin is active high.

1: the INT pin is active low.

0x06

[15:14]

0x0

R/W

Reserved

Write 0x0.

[13:8]

0x00

R/W

FIFO_THRESH

FIFO length threshold. An interrupt is generated when the number of

data-words in the FIFO exceeds the value in FIFO_THRESH. The interrupt pin

automatically deasserts when the number of data-words available in the

FIFO no longer exceeds the value in FIFO_THRESH.

[7:0]

0x00

R/W

Reserved

Write 0x00.

0x08

[15:8]

0x04

REV_NUM

Revision number.

[7:0]

0x16

DEV_ID

Device ID.

ADPD103BCPZ Datasheet(PDF) 47 Page - Analog Devices

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