MIC2126 datasheet(16/34 Pages) MICROCHIP

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MIC2125/6

DS20005459B-page 16

 2015 Microchip Technology Inc.

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

Pin Number

Symbol

Description

1VDD

Internal Linear regulator output. Connect a 4.7 μF ceramic capacitor from VDD to

AGND for decoupling. In the applications where VIN < +5.5V, VDD should be tied to

VIN to by-pass the linear regulator.

2PVDD

5V supply input for the low-side N-channel MOSFET driver, which can be tied to

VDD externally. A 4.7 μF ceramic capacitor from PVDD to PGND is recommended for

decoupling.

3ILIM

Current limit setting input. Connect a resistor from SW to ILIM to set the overcurrent

threshold for the converter.

Low-side gate driver output. The DL driving voltage swings from ground to VDD.

5PGND

Power ground. PGND is the return path for the low side gate driver. Connect PGND

pin to the source of low-side N-Channel external MOSFET.

FREQ

Switching frequency adjust input. Connect FREQ to the mid-point of an external

resistor divider from VIN to GND to program the switching frequency. Tie to VIN to

operate at 750 kHz frequency.

High-side gate driver output. The DH driving voltage is floating on the switch node

voltage (VSW).

Switch node and current-sense input. Connect the SW pin to the switch node of the

buck converter. The SW pin also senses the current by monitoring the voltage

across the low-side MOSFET during OFF time. In order to sense the current

accurately, connect the low-side MOSFET drain to the SW pin using a Kelvin

connection.

BST

Bootstrap Capacitor Input. Connect a ceramic capacitor with a minimum value of

0.1 μF from BST to SW.

OVP

Output Overvoltage Protection Input. Connect to the mid-point of an external

resistive divider from the VOUT to GND to program overvoltage limit. Connect to

AGND if the output overvoltage protection is not required.

No connect.

AGND

Analog Ground. Connect AGND to the exposed pad.

Feedback input. Input to the transconductance amplifier of the control loop. The FB

pin is regulated to 0.6V. A resistor divider connecting the feedback to the output is

used to set the desired output voltage.

Open-drain Power good output. Pull-up with an external pull-up resistor to VDD or to

an external power rail.

Enable input. A logic signal to enable or disable the buck converter operation.

Logic-high enables the device; logic-low shuts down the regulator. In disable mode,

the VDD supply current for the device is minimized to 0.1 µA typically. Do not pull-up

EN pin to VDD/PVDD.

VIN

Supply voltage input. The VIN operating voltage range is from 4.5V to 28V. A 1 μF

ceramic capacitor from VIN to AGND is required for decoupling.

Exposed Pad. Connect the exposed pad to the AGND copper plane to improve the

thermal performance.

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