CL-PD6722 datasheet(49/128 Pages) CIRRUS

49 / 128 page

CL-PD6710/’22

ISA–to–PC-Card Host Adapters

May 1997

PRELIMINARY DATA SHEET v3.1

I/O WINDOW MAPPING REGISTERS

The I/O windows must never include 3E0h and 3E1h.

7.1

I/O Window Control

Bit 0 — I/O Window 0 Size

When bit 1 below is ‘0’, this bit determines the size of the data path to I/O Window 0. When bit 1

is ‘1’, this bit is ignored.

Bit 1 — Auto-Size I/O Window 0

This bit determines the data path to I/O Window 0. Note that when this bit is ‘1’, the -IOIS16 signal

(see page 17) determines the width of the data path to the card.

Bit 3 — Timing Register Select 0

This bit determines the access timing speciﬁcation for I/O Window 0 (see page 72).

Bit 4 — I/O Window 1 Size

When bit 5 below is ‘0’, this bit determines the size of the data path to I/O Window 1. When bit 5

is ‘1’, this bit is ignored.

Bit 5 — Auto-Size I/O Window 1

This bit determines the width of the data path to I/O Window 1. Note that when this bit is ‘1’, the

-IOIS16 signal (see page 17) determines the window size. This bit must be set for proper ATA

mode operation (see Chapter 11).

Index: 07h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Timing

Select 1

Compatibility

Bit

Auto-Size I/O

Window 1

I/O Window 1

Size

Timing

Select 0

Compatibility

Bit

Auto-Size I/O

Window 0

I/O Window 0

Size

RW:0

8-bit data path to I/O Window 0.

16-bit data path to I/O Window 0.

I/O Window 0 Size (see bit 0 above) determines the data path to I/O Window 0.

The data path to I/O Window 0 will be determined based on -IOIS16 returned by the card.

Accesses made with timing speciﬁed in Timing Set 0.

Accesses made with timing speciﬁed in Timing Set 1.

8-bit data path to I/O Window 1.

16-bit data path to I/O Window 1.

I/O Window 1 Size (see bit 4) determines the data path to I/O Window 1.

The data path to I/O Window 1 will be determined based on -IOIS16 returned by the card.

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