CS61535A datasheet(18/48 Pages) CIRRUS

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proximately three Volts. When this threshold is

crossed, the device will delay for about 10 ms to

allow the power supply to reach operating voltage.

After this delay, calibration of the delay lines used

in the transmit and receive sections commences.

The delay lines can be calibrated only if a refer-

ence clock is present. The reference clock for the

receiver is provided by ACLKI (or by the crystal

oscillator if ACLKI is not present). The reference

clock for the transmitter is provided by TCLK. The

initial calibration should take less than 20 ms.

In operation, the delay lines are continuously cali-

brated, making the performance of the device

independent of power supply or temperature vari-

ations. The continuous calibration function

foregoes any requirement to reset the line inter-

face when in operation. However, a reset function

is available which will clear all registers.

In the Hardware and Extended Hardware modes, a

reset request is made by simultaneously setting both

RLOOP and LLOOP high for at least 200 ns. Reset

will initiate on the falling edge of the reset request

(falling edge of RLOOP and LLOOP). In the Host

Mode, a reset is initiated by simultaneously writing

RLOOP and LLOOP to the register. In either mode,

a reset will set all registers to 0 and set LOS high.

Serial Interface

In the Host Mode, pins 23 through 28 serve as a

microprocessor/microcontroller interface. One

eight-bit register can be written to via the SDI pin

or read from the SDO pin at the clock rate deter-

mined by SCLK. Through this register, a host

controller can be used to control operational char-

acteristics and monitor device status. The serial

port read/write timing is independent of the sys-

tem transmit and receive timing.

Data transfers are initiated by taking the chip se-

lect input, CS, low (CS must initially be high).

SCLK may be either high or low when CS in-

itially goes low. Address and input data bits are

clocked in on the rising edge of SCLK. Data on

SDO is valid and stable on the falling edge of

SCLK when CLKE is low, and on the rising edge

of SCLK when CLKE is high. Data transfers are

terminated by setting CS high. CS may go high

no sooner than 50 ns after the rising edge of the

SCLK cycle corresponding to the last write bit.

For a serial data read, CS may go high any time

to terminate the output.

Figure 13 shows the timing relationships for data

transfers when CLKE = 1. When CLKE = 0, data

output from the serial port, SDO, is valid on the

falling edge of SCLK. For CLKE = 1, data bit D7

is held to the falling edge of the 16th clock cycle;

for CLKE = 0, data bit D7 is held to the rising

edge of the 17th clock cycle. SDO goes to a high

SCLK

SDO

SDI

Address/Command Byte

Data Input/Output

R/W

Figure 13. Input/Output Timing

LSB, first bit

R/W

Read/Write Select; 0 = write, 1 =

read

ADD0

LSB of address, Must be 0

ADD1

Must be 0

ADD2

Must be 0

ADD3

Must be 0

ADD4

Must be 1

Reserved - Must be 0

Table 7. Address/Command Byte

CS61535A

DS40F2

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