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GL811USB Datasheet(PDF) 18 Page - List of Unclassifed Manufacturers |
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GL811USB Datasheet(HTML) 18 Page - List of Unclassifed Manufacturers |
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18 / 36 page ![]() GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 17 6.4.2 Multiword DMA data transfer Multiword DMA timing parameters Timing (ns) t0 Cycle time 120 tD DIOR_/ DIOW_ asserted pulse width 80 tE DIOR_ data access - tF DIOR_ data hold - tG DIOR_/ DIOW_ data setup 40 tH DIOW_ data hold 18 tI DMACK to DIOR_/ DIOW_ setup 18 tJ DIOR_/ DIOW_ to DMACK hold 20 tKR DIOR_ negated pulse width 36 tKW DIOW_ negated pulse width 36 tLR DIOR_ to DMARQ delay - tLW DIOW_ to DMARQ delay - tM CS(1:0) (max) valid to DIOR_/ DIOW_ 36 tN CS(1:0) hold 18 tZ DMACK_ to read data released - |
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