7

TH6503 USB Low-Speed Interface

Input signals are double buffered and digital filtered. Therefore all spikes with a width < 255 ns are

suppressed.

Timing Serial

Interface

(continued)

Description [1]

Symbol

Unit

min

typ

max

General

Oscillator Input period on OSC1

ns

164

170

Rising time of SDO

t

1

ns

20

Falling time of SDO

t

2

ns

7

SCK period

t

3

ns

600

Step

High time SCK [2]

t

4

ns

345

Low time SCK [2, 3]

t

5

ns

255

Data IN

Setup time of SCK after rising edge of SIN

t

6

ns

170

Hold time of SIN after last rising edge of SCK

t

7

ns

170

Setup time of INT-Signal after rising edge of SIN

t

8

ns

200

Hold time of INT-Signal after falling edge of SIN

t

9

ns

165

Setup time of Data on SDI before rising edge of SCK

t

10

ns

170

Hold time of Data on SDI after falling edge of SCK

t

11

ns

0

Data OUT

Setup time of SDI-pulse after falling edge of SIN

t

12

ns

170

Setup time of SIN after last falling edge of SCK

t

13

ns

170

High time of SDI-pulse

t

14

ns

255

Setup time of Data on SDO after falling edge of SDI-pulse

t

15

ns

280

Setup time of SCK after falling edge of SDI-pulse

t

16

ns

170

Setup time of Data on SDO after falling edge of SCK

t

17

ns

365

Notes:

[1] Capacitive load of 50 pF

[2] Can be asymmetrical

[3] The low time of SCK between the last bit of a byte and the first bit of the next byte must be at least 510 ns.