0.1 F

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Reduce logic signal trace

when possible

4B

4A

4Y

G

3Y

3A

3B

2B

2A

2Y

G

1Y

1A

1B

Termination Resistor

14

SN65LBC173A-EP

SLLSEH1 – NOVEMBER 2016

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Product Folder Links: SN65LBC173A-EP

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Copyright © 2016, Texas Instruments Incorporated

10 Power Supply Recommendations

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-

impedance power supplies.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the

operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance

power sources local to the analog circuitry.

•

Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to

the device as possible.

•

Place termination resistor as close as possible to the input pins (if end point node).

•

Keep trace lengths from input pins to buss as short as possible to reduce stub lengths and reflections on any

nodes that are not end points of bus.

•

To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as

opposed to in parallel with the noisy trace.

11.2 Layout Example

Figure 14. Layout with PCB Recommendations