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STM32F745VG Datasheet(PDF) 204 Page - STMicroelectronics |
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STM32F745VG Datasheet(HTML) 204 Page - STMicroelectronics |
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204 / 227 page  Package information STM32F745xx STM32F746xx 204/227 DocID027590 Rev 4 Marking of engineering samples The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 87. WLCSP143, 0.4 mm pitch wafer level chip scale package top view example 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. Table 116. WLCSP143 recommended PCB design rules Dimension Recommended values Pitch 0.4 Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm |
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