SRAM

AS5LC1008

AS5LC1008

Rev. 1.4 10/13

Micross Components reserves the right to change products or specifications without notice.

7

o

(CE\ Controlled, OE\ = HIGH or LOW)

NOTES:

1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified

in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE\ LOW and WE\ LOW. All signals must be in valid states to initiate a Write, but any one can go

inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.

-10

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX UNITS

Write Cycle Time

10

---

12

---

15

---

20

---

ns

CE\ to Write End

7

---

8

---

9

---

10

---

ns

Address Setup Time to Write End

8

---

9

---

10

---

12

---

ns

Address Hold from Write End

0

---

0

---

0

---

0

---

ns

Address Setup Time

0

---

0

---

0

---

0

---

ns

WE\ Pulse Width (OE\ HIGH)

1

7

---

8

---

9

---

10

---

ns

WE\ Pulse Width (OE\ LOW)

2

10

---

12

---

12

---

15

---

ns

Data Setup to Write End

5

---

6

---

7

---

8

---

ns

Data Hold to Write End

0

---

0

---

0

---

0

---

ns

WE\ LOW to High-Z Output

2

---

5

---

6

---

7

---

8

ns

WE\ HIGH to Low-Z Output

2

2

---

2

---

2

---

2

---

ns

-20

-12

-15