HV7350

DS20005627A-page 8

 2016 Microchip Technology Inc.

30

TX7

31

RGND

Damping ground and bleed resistors common return ground

32

TX6

33

RGND

Damping ground and bleed resistors common return ground

34

TX5

35

CNEG

Built-in linear voltage –5V regulator output decoupling capacitor pin, 1 uF from CNEG to GND

36

CPOS

Built-in linear voltage +5V regulator output decoupling capacitor pin, 1 uF from CPOS to GND

37

TX4

38

RGND

Damping ground and bleed resistors common return ground

39

TX3

40

RGND

Damping ground and bleed resistors common return ground

41

TX2

42

RGND

Damping ground and bleed resistors common return ground

43

TX1

44

VNN

Negative high-voltage power supply (–10V to –60V)

45

VNN

46

VNN

47

CNF

Built-in linear voltage VNF regulator output decoupling capacitor pin, 1 uF from CNF to VNN for every CNF

pin

48

CPF

Built-in linear voltage VPF regulator output decoupling capacitor pin, 1 uF from VPP to CPF for every CPF pin

49

VPP

Positive high-voltage power supply (+10V to +60V)

50

VPP

51

VPP

52

VDD

Positive voltage power supply (+3.3V)

53

GND

Logic and circuit return ground (0V)

54

CLK

Retiming register clock input. Connect to VLL to disable the retiming function.

55

PIN1

Input logic control of high-voltage output P-FET for Channel 1; High = on; Low = off

(See Logic Control Table.)

56

NIN1

Input logic control of high-voltage output N-FET for Channel 1; High = on; Low = off

(See Logic Control Table.)

VSUB

(Thermal Pad)

Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be con-

nected to GND (0V) externally.

TABLE 2-1:

PAD FUNCTION TABLE (CONTINUED)

Pin

Number

Pin

Name

Description