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© IMP, Inc.

Process C1210

Starting Material

EPI P <100>

N+/P+ Width/Space

2.5/ 2.0

µm

Starting Mat. Resistivity

7 - 8.5

Ω-cm

N+ To P+ Space

9.0

µm

Typ. Operating Voltage

5V

Contact To Poly Space

1.5

µm

Well Type

N-well

Contact Overlap Of Diffusion

1.0

µm

Metal Layers

2

Contact Overlap Of Poly

1.0

µm

Poly Layers

2

Metal-1 Overlap Of Contact

1.0

µm

Contact Size

1.5x1.5

µm

Metal-1 Overlap Of Via

1.0

µm

Via Size

1.5x1.5

µm

Metal-2 Overlap Of Via

1.0

µm

Metal-1 Width/Space

2.5 / 1.5

µm

Minimum Pad Opening

65x65

µm

Metal-2 Width/Space

2.5 / 1.5

µm

Minimum Pad-to-Pad Spacing

5.0

µm

Gate Poly Width/Space

1.5 / 2.0

µm

Minimum Pad Pitch

80.0

µm

Special Feature of C1210 Process: This process offers zero threshold n- and p-channel

transistors in addition to normal threshold transistors of CMOS 1.2

µm technology.

Physical Characteristics

Metal 2

Metal 1

VIA

Metal 1

LTO

p

p

Field Oxide

N-well

LTO

5.5

VGS = 4.0V

VGS = 3.0V

VGS = 2.0V

VGS = 1.0V

VGS = 0V

ID vs VD, W/L = 20/1.2

.00

012345

0.55 mA

/div

Drain Voltage (v) VDS

n-ch Transistor IV characteristics of a 20/1.2 device

-3.0

VGS = –5.0V

VGS = –4.0V

VGS = –3.0V

VGS = –2.0V

VGS = –1.0V

VGS = 0.0V

ID vs VD, W/L = 20/1.2

.00

0

–1–2–3

– 4–5

0.3 mA

/div

Drain Voltage (v) VDS

p-ch Transistor IV characteristics of a 20/1.2 device

Cross-Sectional view of the LVMOS process