LAN9250 datasheet(105/421 Pages) MICROCHIP

105 / 421 page

 2015 Microchip Technology Inc.

DS00001913A-page 105

LAN9250

8-BIT READ AND WRITE

For writes, the address is set to access the lower BYTE of one of the Index Registers and FIFOSEL is held low. Data

on D[7:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven. The cycle repeats for the remaining

BYTEs of the Index Register, if desired by the host.

For reads, the address is set to access the lower BYTE of one of the Index Registers and FIFOSEL is held low. Read

data is driven on D[7:0] during RD active. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs

of the Index Register, if desired by the host.

FIGURE 9-27:

INDEXED ADDRESSING INDEX REGISTER ACCESS - 16-BIT WRITE/READ

Note:

The upper WORD of Index Registers is reserved and don’t care. Therefore reads and writes to those

BYTEs are not useful.

FIGURE 9-28:

INDEXED ADDRESSING INDEX REGISTER ACCESS - 8-BIT WRITE/READ

INDEX,1'b0

Index 15:8

D[15:8]

A[4:1]

INDEX,1'b1

8'hXX

Index 7:0

D[7:0]

8'hXX

FIFOSEL

INDEX,1'b0

Index 15:8

Index 7:0

INDEX,1'b1

8'hXX

INDEX,2'b00

D[15:8]

A[4:0]

INDEX,2'b01

Index 7:0

D[7:0]

Index 15:8

FIFOSEL

INDEX,2'b00

INDEX,2'b01

INDEX,2'b10

INDEX,2'b11

8'hXX

Hi-Z

Index 7:0

Index 15:8

8'hXX

INDEX,2'b10

INDEX,2'b11

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