17

COMMERCIALTEMPERATURERANGE

BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36

Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)

NOTE:

1. CSA = LOW, W/RA = HIGH, MBA = LOW.

Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT

Modes)

NOTES:

1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FF/IR is set HIGH.

2. Programmable offsets are written serially to the SD input in the order AF offset (Y) and AE offset (X).

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CLKA

RS1

FF/IR

A0-A35

FS1,FS0

ENA

4

0,0

AF Offset

(Y)

AE Offset

(X)

First Word to FIFO1

FS2

1

2

CLKA

FF/IR

FS1/

SEN

AE Offset

(X) LSB

AF Offset

(Y) MSB

RS1

4

FS2

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