IDT72V3653_16 datasheet(14/30 Pages) IDT

14 / 30 page

COMMERCIALTEMPERATURERANGE

IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH

BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36

firstsynchronizationcycleifitoccursattimetSKEW2orgreaterafterthereadthat

reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)].

Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-

nization cycle (see Figure 16).

MAILBOX REGISTERS

Two36-bitbypassregistersareontheIDT72V3653/72V3663/72V3673

topasscommandandcontrolinformationbetweenPortAandPortBwithout

puttingitinqueue.TheMailboxselect(MBA,MBB)inputschoosebetweena

mail register and a FIFO for a port data transfer operation. The usable width

ofboththeMail1andMail2RegistersmatchestheselectedbussizeforPortB.

ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen

a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the

selectedPortBbussizeis36bits,theusablewidthoftheMail1Registeremploys

datalinesA0-A35.IftheselectedPortBbussizeis18bits,thentheusablewidth

of the Mail1 Register employs data lines A0-A17. (In this case, A18-A35 are

don’tcareinputs.)IftheselectedPortBbussizeis9bits,thentheusablewidth

oftheMail1RegisteremploysdatalinesA0-A8.(Inthiscase,A9-A35aredon’t

careinputs.)

A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2

HIGH. If the selected Port B bus size is 36 bits, the usable width of the Mail2

employsdatalinesB0-B35.IftheselectedPortBbussizeis18bits,thenthe

usablewidthoftheMail2RegisteremploysdatalinesB0-B17.(Inthiscase,B18-

B35aredon’tcareinputs.)IftheselectedPortBbussizeis9bits,thentheusable

widthoftheMail2RegisteremploysdatalinesB0-B8.(Inthiscase,B9-B35are

don’tcareinputs.)

Writing data to a mail register sets its corresponding flag (MBF1 or

MBF2)LOW.Attemptedwritestoamailregisterareignoredwhilethemailflag

isLOW.

When data outputs of a port are active, the data on the bus comes from

theFIFOoutputregisterwhentheportMailboxselectinputisLOWandfrom

the mail register when the port Mailbox select input is HIGH.

The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH

transition on CLKB when a Port B read is selected by CSB, W/RB, and ENB

with MBB HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on

B0-B35.Foran18-bitbussize,18bitsofmailboxdataareplacedonB0-B17.

(Inthiscase,B18-B35areindeterminate.)Fora9-bitbussize,9bitsofmailbox

data are placed on B0-B8. (In this case, B9-B35 are indeterminate.)

The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH

transition on CLKA when a Port A read is selected by CSA, W/RA, and ENA

with MBA HIGH.

For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For

an18-bitbussize,18bitsofmailboxdataareplacedonA0-A17.(Inthiscase,

A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are

placed on A0-A8. (In this case, A9-A35 are indeterminate.)

Thedatainamailregisterremainsintactafteritisreadandchangesonly

whennewdataiswrittentotheregister.TheEndianselectfeaturehasnoeffect

onmailboxdata. Formailregisterandmailregisterflagtimingdiagrams,see

Figure 17 and 18.

BUS SIZING

The Port B bus can be configured in a 36-bit long word, 18-bit word, or

9-bitbyteformatfordatareadfromtheFIFO. ThelevelsappliedtothePortB

BusSizeselect(SIZE)andtheBus-Matchselect(BM)determinethePortBbus

size. TheselevelsshouldbestaticthroughoutFIFOoperation. Bothbussize

selectionsareimplementedatthecompletionofReset,bythetimetheFull/Input

Ready flag is set HIGH, as shown in Figure 2.

TwodifferentmethodsforsequencingdatatransferareavailableforPort

B when the bus size selection is either byte-or word-size. They are referred

toasBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificant

bytefirst). ThelevelappliedtotheBig-Endianselect(BE)inputduringtheLOW-

to-HIGHtransitionofRS1selectstheendianmethodthatwillbeactiveduring

FIFO operation. BE is a don’t care input when the bus size selected for Port

Bislongword. TheendianmethodisimplementedatthecompletionofReset,

by the time the Full/Input Ready flag is set HIGH, as shown in Figure 2.

Only 36-bit long word data is written to or read from the FIFO memory on

the IDT72V3653/72V3663/72V3673. Bus-matching operations are done after

data is read from the FIFO RAM. These bus-matching operations are not

available when transferring data via mailbox registers. Furthermore, both the

word-andbyte-sizebusselectionslimitthewidthofthedatabusthatcanbeused

for mail register operations. In this case, only those byte lanes belonging to the

selected word- or byte-size bus can carry mailbox data. The remaining data

outputswillbeindeterminate. Theremainingdatainputswillbedon’tcareinputs.

For example, when a word-size bus is selected, then mailbox data can be

transmitted only between A0-A17 and B0-B17. When a byte-size bus is

selected, then mailbox data can be transmitted only between A0-A8 and B0-

B8. (See Figures 17 and 18).

BUS-MATCHING FIFO READS

Data is read from the FIFO RAM in 36-bit long word increments. If a long

wordbussizeisimplemented,theentirelongwordimmediatelyshiftstotheFIFO

output register. If byte or word size is implemented on Port B, only the first one

or two bytes appear on the selected portion of the FIFO output register, with the

rest of the long word stored in auxiliary registers. In this case, subsequent FIFO

reads output the rest of the long word to the FIFO output register in the order

shown by Figure 2.

WhenreadingdatafromFIFOinbyteorwordformat,theunusedB0-B35

outputsareindeterminate.

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