WM8944BECSSLASHR datasheet(67/165 Pages) CIRRUS

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WM8944B

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

Clock Gen

control

3:1

BCLK_DIV [2:0]

011

BCLK Frequency (Master mode)

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 4

011 = SYSCLK / 8

100 = SYSCLK / 16

101 = SYSCLK / 32

110 = reserved

111 = reserved

MSTR

Digital Audio Interface Mode select

0 = Slave mode

1 = Master mode

Table 44 Digital Audio Interface Control

AUDIO DATA FORMATS

Three basic audio data formats are supported:



Left justified



I2S



DSP mode

All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the

Electrical Characteristic section for timing information.

PCM operation is supported using the DSP mode.

The WM8944B is largely a mono device. In the default configuration, the WM8944B transmits ADC

data on the Left channel only of the Digital Audio Interface, and receives DAC data on the Left

channel. The WM8944B also supports a stereo digital microphone interface, enabling stereo output on

the digital audio interface (ADCDAT pin).

The digital audio interface transmit configuration can be set using the ADCR_SRC and ADCL_SRC

bits; the DAC receive channel can be selected using the DAC_SRC bit. Digital inversion of the ADC

and DAC data is also possible.

The register bits controlling audio data format and channel configuration are described in Table 45.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (04h)

Audio

Interface

ADCR_SRC

Right Digital Audio interface source

0 = ADC / Left DMIC data is output

on right channel

1 = Right DMIC data is output on

right channel

ADCL_SRC

Left Digital Audio interface source

0 = ADC / Left DMIC data is output

on left channel

1 = Right DMIC data is output on

left channel

DAC_SRC

DAC Data Source Select

0 = DAC outputs left interface data

1 = DAC outputs right interface data

BCLK_INV

BCLK Invert

0 = BCLK not inverted

1 = BCLK inverted

WM8944BECS/R Datasheet(PDF) 67 Page - Cirrus Logic

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