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TMS320C51 Datasheet(PDF) 39 Page - Texas Instruments |
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TMS320C51 Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 87 page  TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 39 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 instruction set summary (continued) Table 7. TMS320C5x Instruction Set Opcodes (Continued) ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS (CONTINUED) INSTRUCTION MNEMONIC OPCODE WORDS CYCLES Subtract from ACC with borrow Conditional subtract Subtract from ACC with sign extension suppressed Subtract from ACC, shift specified by TREG1 [3 – 0] XOR ACC with data value XOR with ACC long immediate with shift XOR with ACC long immediate with shift of 16 XOR ACCB with ACC Zero ACC, load high ACC with rounding Zero ACC and product register SUBB SUBC SUBS SUBT XOR XOR XOR XORB ZALR ZAP 0110 0100 IAAA AAAA 0000 1010 IAAA AAAA 0110 0110 IAAA AAAA 0110 0111 IAAA AAAA 0110 1100 IAAA AAAA 1011 1111 1101 SHFT 1011 1110 1000 0011 1011 1110 0001 1010 0110 1000 IAAA AAAA 1011 1110 0101 1001 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 2 2 1 1 1 AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS INSTRUCTION MNEMONIC OPCODE WORDS CYCLES Add to AR short immediate Compare AR with CMPR Load AR from addressed data Load AR short immediate Load AR long immediate Load data page pointer with addressed data Load data page immediate Modify auxiliary register Store AR to addressed data Subtract from AR short immediate ADRK CMPR LAR LAR LAR LDP LDP MAR SAR SBRK 0111 1000 IIII IIII 1011 1111 0100 01CM 0000 0ARX IAAA AAAA 1011 0ARX IIII IIII 1011 1111 0000 1ARX 0000 1101 IAAA AAAA 1011 110I IIII IIII 1000 1011 IAAA AAAA 1000 0ARX IAAA AAAA 0111 1100 IIII IIII 1 1 1 1 2 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 BRANCH INSTRUCTIONS INSTRUCTION MNEMONIC OPCODE WORDS CYCLES Branch unconditional with AR update Branch addressed by ACC Branch addressed by ACC delayed Branch AR ≠ 0 with AR update Branch AR ≠ 0 with AR update delayed Branch conditional Branch conditional delayed Branch unconditional with AR update delayed Call subroutine addressed by ACC Call subroutine addressed by ACC delayed Call unconditional with AR update Call unconditional with AR update delayed Call conditional Call conditional delayed Software interrupt Nonmaskable interrupt Return Return conditional Return conditionally, delayed Return, delayed Return from interrupt with enable Return from interrupt Trap Execute next one or two INST on condition B BACC BACCD BANZ BANZD BCND BCNDD BD CALA CALAD CALL CALLD CC CCD INTR NMI RET RETC RETCD RETD RETE RETI TRAP XC 0111 1001 1AAA AAAA 1011 1110 0010 0000 1011 1110 0010 0001 0111 1011 1AAA AAAA 0111 1111 1AAA AAAA 1110 00TP ZLVC ZLVC 1111 00TP ZLVC ZLVC 0111 1101 1AAA AAAA 1011 1110 0011 0000 1011 1110 0011 1101 0111 1010 1AAA AAAA 0111 1110 1AAA AAAA 1110 10TP ZLVC ZLVC 1111 10TP ZLVC ZLVC 1011 1110 011 I NTR# 1011 1110 0101 0010 1110 1111 0000 0000 1110 11TP ZLVC ZLVC 1111 11TP ZLVC ZLVC 1111 1111 0000 0000 1011 1110 0011 1010 1011 1110 0011 1000 1011 1110 0101 0001 111N 01TP ZLVC ZLVC 2 1 1 2 2 2 2 2 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 4 4 2 2 or 4 2 2 or 4 2 2 4 2 4 2 2 or 4 2 4 4 4 2 or 4 2 2 4 4 4 1 instruction set summary (continued) Table 7. TMS320C5x Instruction Set Opcodes (Continued) |
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