TMS320C51 datasheet(72/87 Pages) TI

72 / 87 page

TMS320C5x, TMS320LC5x

DIGITAL SIGNAL PROCESSORS

SPRS030A – APRIL 1995 – REVISED APRIL 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SERIAL-PORT RECEIVE TIMING IN TDM MODE

timing requirements over recommended ranges of supply voltage and operating ambient-air

temperature [H = 0.5tc(CO)] (see Figure 25)

’320C5x-40

’320C5x-57

’320LC5x-40

’320LC5x-50

’320C5x-80

’320LC5x-80

’320C5x-100

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tc(SCK)

Cycle time, serial-port clock

5.2H†

‡

5.2H†

‡

5.2H§

‡

tf(SCK)

Fall time, serial-port clock

8¶

tr(SCK)

Rise time, serial-port clock

8¶

tw(SCK)

Pulse duration, serial-port clock low/high

2.1H†

tsu(TD-TCH)

Setup time, TDAT before TCLK rising edge

th(TCH-TD)

Hold time, TDAT after TCLK rising edge

–3

–2

tsu(TA-TCH)

Setup time, TADD before TCLK rising edge#

th(TCH-TA)

Hold time, TADD after TCLK rising edge#

–3

–2

tsu(TF-TCH)

Setup time, TFRM before TCLK rising edge§

th(TCH-TF)

Hold time, TFRM after TCLK rising edge§

† Values ensured by design and are not tested

‡ The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

§ TFRM timing and waveforms shown in Figure 25 are for external TFRM. TFRM also can be configured as internal. The TFRM internal case is

illustrated in the transmit timing diagram in Figure 26.

¶ Values derived from characterization data and not tested

# These parameters apply only to the first bits in the serial bit string.

B12

B13

B14

B15

tw(SCK)

tsu(TD-TCH)

th(TCH-TD)

tsu(TA-TCH)

th(TCH-TA)

tr(SCK)

tf(SCK)

tc(SCK)

TFRM

TADD

TDAT

TCLK

th(TCH-TF)

tsu(TF-TCH)

th(TCH-TA)

Figure 25. Serial-Port Receive Timing in TDM Mode

TMS320C51 Datasheet(PDF) 72 Page - Texas Instruments

TMS320C51 Datasheet(HTML) 72 Page - Texas Instruments

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