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DLPR910 Datasheet(PDF) 4 Page - Texas Instruments |
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DLPR910 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 17 page  4 DLPR910 DLPS065B – SEPTEMBER 2015 – REVISED NOVEMBER 2016 www.ti.com Product Folder Links: DLPR910 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. BUSY C1 — Do Not Connect. Leave unconnected. CLKOUT C2 — Do Not Connect. Leave unconnected. DNC C3 — Do Not Connect. Leave unconnected. DNC C4 — Do Not Connect. Leave unconnected. D4 C5 — Do Not Connect. Leave unconnected. VCCO C6 P Positive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and internal buffers. ( CF) D1 I Configuration pin. The (CF) pin must be pulled High using an external 4.7-kΩ pull-up to VCCO. Selects serial mode configuration. (CEO) D2 — Do Not Connect. Leave unconnected. DNC D3 — Do Not Connect. Leave unconnected. DNC D4 — Do Not Connect. Leave unconnected. D3 D5 — Do Not Connect. Leave unconnected. VCCO D6 P Positive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and internal buffers. VCCINT E1 P Positive 1.8-V supply voltage for internal logic. TMS E2 I JTAG Mode Select Input. TMS has an internal 50-kΩ resistive pull-up to VCCJ. DNC E3 — Do Not Connect. Leave unconnected. DNC E4 — Do Not Connect. Leave unconnected. D2 E5 — Do Not Connect. Leave unconnected. TDO E6 O JTAG Serial Data Output. TDO has an internal 50-kΩ resistive pull-up to VCCJ. GND F1 G Ground DNC F2 — Do Not Connect. Leave unconnected. DNC F3 — Do Not Connect. Leave unconnected. DNC F4 — Do Not Connect. Leave unconnected. GND F5 G Ground GND F6 G Ground TDI G1 I JTAG Serial Data Input. TDI has an internal 50k-Ω resistive pull-up to VCCJ. DNC G2 — Do Not Connect. Leave unconnected. REV_SEL0 G3 I Revision Select [1:0] Inputs. When the (EN_EXT_SEL) is Low, the Revision Select pins are used to select the design revision to be enabled. The Revision Select [1:0] inputs have an internal 50-kΩ resistive pull-up to VCCO. The (REV_SEL0) pin must be pulled Low using an external 10-kΩ pull-down to Ground. The (REV_SEL1) pin must be connected to Ground. REV_SEL1 G4 I VCCO G5 P Positive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and internal buffers. VCCINT G6 P Positive 1.8-V supply voltage for internal logic. GND H1 G Ground VCCJ H2 P Positive 3.3-V JTAG I/O supply voltage connected to the TDO output voltage driver and TCK, TMS and TDI input buffers. TCK H3 I JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. (EN_EXT_SEL) H4 I External Selection Input. (EN_EXT_SEL) has an internal 50-kΩ resistive pull- up to VCCO. The (EN_EXT_SEL) pin must be connected to Ground. D1 H5 — Do Not Connect. Leave unconnected. D0 H6 O DATA output pin to provide data for configuring the DLPC910 in serial mode. |
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